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Toshiba’s newly developed fully isolated N-channel LDMOS realizes high HBM robustness and high breakdown voltage to negative bias in 0.13-micron generation analog power semiconductors

June 1, 2017

Toshiba Corporation

Storage & Electronic Devices Solutions Company

Toshiba has developed fully isolated N-channel LDMOS*1 technology that overcomes the trade-off between breakdown voltage to negative bias (BVnb) and HBM*2 robustness, a measure of resistance to electrostatic discharge (ESD). Details of this achievement were reported on June 1 at ISPSD 2017 (International Symposium on Power Semiconductor Devices and ICs 2017), an IEEE-sponsored international conference on power semiconductors, held in Japan.

Recent years have seen an increasing need for automotive analog ICs and Power ICs with fully isolated Nch-LDMOS and high BVnb, especially devices supporting voltages of 40V and over. Achieving a higher BVnb has until now required a trade-off with securing HBM robustness, and achieving both has required a bigger die, in order to electrically isolate substrates and the inside of the die. This has impeded progress in miniaturization and cost reduction. Furthermore, since HBM robustness is a parameter that is difficult to estimate without actually fabricating devices, a new parameter for estimating HBM robustness was strongly required.

In order to overcome the trade-off between HBM robustness and BVnb while minimizing die size, Toshiba conducted 2D TCAD simulations of numerous parameters and found that current flow concentration, which corresponds to the peak value of the electric field under the drain region (EUD*3), depends on HBM robustness. As a result of utilizing EUD to optimize die characteristics by adjusting various parameters, Toshiba successfully improved HBM robustness while achieving a rated voltage of 25 to 96V. This also realized a die size reduction of 46% for 80V fully isolated Nch-LDMOS products, satisfying HBM +/-4kV, a measure of HBM robustness.

Toshiba has produced prototypes of BiCD-0.13G3 process-based*4 devices using the new technology and plans to start mass production in fiscal year 2018. The company is committed to contributing to the realization of lighter, more efficient automobiles and improving their performance by expanding the range of products offering fully isolated Nch-LDMOS.

*1 Fully isolated N-channel LDMOS: A laterally diffused MOS transistor with a structure that reduces the electric field between the drain and gate by fully isolating them electrically.

*2 HBM (Human Body Model): a model for characterizing the susceptibility of electronic devices to ESD, based on ESD from the human body.

*3 EUD (Electrical field under Drain region): Electric field strength observed under the drain source.

*4 BiCD-0.13G3 process technology: One of Toshiba’s power semiconductor process technologies. Users can select the process that suits their application: BiCD-0.13G1/G2/G3, mainly for automotive devices; CD-0.13G3, mainly for motor control drivers; and CD-0.13G1/G2, mainly for power management IC.

Fig.1. Cross-sectional structure of fully isolated Nch-LDMOS
Fig.1. Cross-sectional structure of fully isolated Nch-LDMOS

Fig.2. Relationship between EUD and HBM Robustness
Fig.2. Relationship between EUD and HBM Robustness

Information in this document, including product prices and specifications, content of services and contact information, is correct on the date of the announcement but is subject to change without prior notice.

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