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The TMPV7608XBG is new addition to the Visconti™4 (TMPV760) Series optimized for use in next-generation advanced driver assistance systems (ADAS), which require new vehicles to have a safety feature designed to avoid pedestrian collisions in both day time and night time conditions that will be part of the European New Car Assessment Programme (Euro NCAP).
The TMPV7608XBG allows an ADAS to realize nighttime pedestrian detection as reliable as daytime pedestrian detection available with conventional vision systems. Toshiba’s original Enhanced CoHOG (Co-occurrence Histograms of Oriented Gradients) accelerators combine luminance-based CoHOG feature descriptors with color-based feature descriptors obtained using a newly developed technique. This enhancement leads to a remarkable improvement in the recognition accuracy, especially at nighttime and at scenes with less luminance differences between objects and the background. Additionally, the Enhanced CoHOG accelerators deliver outstanding computational performance, reducing the time taken for recognition.
The TMPV7608XBG incorporates a Structure from Motion (SfM) accelerator that allows detection of general stationary obstacles such as fallen objects and landslides. The SfM accelerator provides three-dimensional (3D) estimates of the distance to, and the height and width of, the stationary obstacles, based on a sequence of images from a monocular camera. This accelerator makes it possible to detect any stationary obstacles without a learning curve, as well as moving objects (using motion analysis) and a particular class of objects such as pedestrians and vehicles (using pattern recognition). The use of 3D information helps reduce the region of interest (ROI) in recognized objects and thus improve the pattern recognition speed, delivering faster driving assistance and control.
The TMPV7608XBG incorporates eight new image processing engines called Media Processing Engines (MPEs) with a double-precision floating-point unit, and various image processing accelerators, numbering 14 in all, to achieve 10 times* the image processing performance of the conventional product. Consequently, the TMPV7608XBG allows parallel execution of up to eight image recognition applications. All the image processing engines and accelerators can recognize pedestrians and vehicles simultaneously in 50 milliseconds, running at a clock frequency of up to 266.7 MHz.
* Comparison with the previous Toshiba model
A performance comparison of a new and conventional products
* The video input interface of the TMPV7608XBG has a 4-of-8 video switch.
Example of the basic system configuration for the TMPV7608XBG
| Series Name / Product Name | Visconti4 / TMPV7608XBG | |
|---|---|---|
| CPUs | Toshiba original 32-bit RISC Media embedded Processor (MeP) x 2 sets |
|
| Image Processing Engines | Toshiba original 32-bit RISC Media Processing Engine Media Processing Engine (MPE) with Double-precision FPU x 8 sets with 256 KB L2 cache x 2 sets |
|
| Image Processing Accelerators | Affine Transformation | 3 ch (Lens Undistortion, Affine Transformation, Viewpoint Conversion, etc.) |
| Filter | 2 ch (Smoothing, Edge Detection, Corner Detection, Oriented Gradient Computation, Color Space Conversion, Demosaicing, etc.) | |
| Histogram | 1 ch (Histogram, Image Conversion using LUT, etc.) | |
| Histogram of Oriented Gradients(HOG) | 1 ch (HOG/CoHOG Features + Linear Support Vector Machine) | |
| Enhanced CoHOG | 2 ch (HOG/CoHOG/Color-CoHOG Features etc. + Linear Support Vector Machine) | |
| Matching | 2 ch (Tracking, Motion Detection) | |
| Pyramid | 2ch (Pyramid Image Generation) | |
| Structure from Motion (SfM) | 1ch (3D Reconstruction) | |
| On-chip Memories | Masked ROM | 80 KBytes |
| SRAM | 1632 KBytes | |
| On-chip Peripherals | Video Input Interface | Up to 8 ch (CMOS I/F: Up to 4 ch / max. SXGA, 60fps | MIPI® CSI-2 I/F: Up to 4ch / max. 1080p, 60fps) with Video Switch (8-input to 4-select) |
| Video Output Interface | 1 ch | |
| External Memory Controllers | DDR SDRAM Controller LPDDR2-800 | |
| Serial NOR Memory Controller (Single or Quad SPI) | ||
| Parallel SRAM / NOR Memory Controller | ||
| External MCU Interface | 1 ch (8-bit bidirectional parallel input/output) | |
| General-Purpose I/O | 24-bits | |
| CAN Controllers | 3 ch | |
| I2C Interface | Up to 8 ch | |
| UART Interface | Up to 5 ch (1ch for debug use only) | |
| SPI Interface | Up to 4 ch | |
| PCM Interface | Up to 2 ch | |
| Timer / Counters | 32 ch | |
| Operating Frequency | 266.7 MHz max. | |
| Operating Voltage | Core: 1.1 V, I/O: 3.3 V, 1.2 V (for LPDDR2 SDRAM) / 1.2V (MIPI® CSI-2 I/F) |
|
| Package | P-FBGA 796-ball, 27mm x 27mm, 0.8 mm ball pitch | |
Product Lineup (Parametric Search)
View the product list of image recognition processors to find products that meet your performance specifications.
* MIPI is a registered trademark owned by the MIPI Alliance.
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* MediaLB and MOST are registered trademarks of Microchip Technology Inc. in the United States and other countries.
* Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
* All other company names, product names, and service names mentioned herein may be trademarks of their respective companies.
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