FFSA™ is an innovative custom SoC development platform that presents metal configurable standard cell logic gates, SRAM, high-speed SerDes protocols and input/output buffers capable of meeting the needs of diverse customers.
The upper metal layers are reserved for customization, while the other layers are common to all customers . This enables a proportion of the device masks to be prepared in advance, thus reducing both development and production time, and allows the largest part of the overall cost to be shared among many different customizations, resulting in much lower NRE than for individual ASIC development.
By using ASIC development methodology and a cell library, its performance and power consumption level are nearly equivalent to those of ASIC.
Moreover, with customization limited to only a few metal layers, turnaround time of sample manufacturing and mass production can be shorter than for ASIC.
FFSA™ can perform with more than double the frequency (SRAM) compared with the same process node FPGA.
FFSA™ can achieve 5 times the power efficiency compared with FPGA one process node ahead.
*The result varies depending on design and conditions.
We have multiple masterslices with multiprotocol high-speed SerDes for each process and propose the optimal masterslice to meet the customer’s requirement.
|Process Technology||SerDes (Transceiver)||Gate Count (Max)||SRAM (Max)||I/O (Max)|
|Speed (Max)||Lane (Max)|
FFSA™ metal configurable technology is applicable as an IP for ASIC development.
This means customers are able to develop their own original masterslices with a mix of highly optimized ASIC blocks and metal configurable FFSA™ blocks, and reuse the original masterslices to develop variants only with the change of metal layers, resulting in total NRE reduction and flexible ASIC-style implementation.
* All other company names, product names, and service names mentioned herein may be trademarks of their respective companies.