TMPM4G(1) Group Peripheral Driver User Manual  V1.0.0.0
txz_hdma_include.h
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1 
13 /*------------------------------------------------------------------------------*/
14 /* Define to prevent recursive inclusion */
15 /*------------------------------------------------------------------------------*/
16 #ifndef __HDMA_INCLUDE_H
17 #define __HDMA_INCLUDE_H
18 
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22 
23 /*------------------------------------------------------------------------------*/
24 /* Includes */
25 /*------------------------------------------------------------------------------*/
26 #include "txz_driver_def.h"
27 
37 /*------------------------------------------------------------------------------*/
38 /* Macro Function */
39 /*------------------------------------------------------------------------------*/
45 /* no define */
46  /* End of group HDMA_Private_macro */
50 
51 
52 /*------------------------------------------------------------------------------*/
53 /* Macro Definition */
54 /*------------------------------------------------------------------------------*/
65 #define HDMA_NULL ((void *)0)
66  /* End of group HDMA_NullPointer */
69 
75 #define HDMA_PARAM_OK ((int32_t)1)
76 #define HDMA_PARAM_NG ((int32_t)0) /* End of group HDMA_ParameterResult */
80 
81 
87 #define HDMA_CHANNEL_0 ((int32_t)0)
88 #define HDMA_CHANNEL_1 ((int32_t)1) /* End of group HDMA_Channel */
92 
102 /* E */
108 #define HDMA_CIRCUIT_DISABLE ((uint32_t)0x00000000)
109 #define HDMA_CIRCUIT_ENABLE ((uint32_t)0x00000001) /* End of group HDMA_Circuit*/
113  /* End of group HDMAxCfg */
116 
142 /* softb_req_mask_set */
143 #define SOFTBREQMASKSET_ALL_MASK ((uint32_t)0x0000FFFF)
144 #define SOFTBREQMASKSET_ALL_CLR ((uint32_t)0x00000000) /* End of group HDMAxSoftBReqMaskSet */
148 
174 /* softs_req_mask_set */
175 #define SOFTSREQMASKSET_ALL_MASK ((uint32_t)0x0000FFFF)
176 #define SOFTSREQMASKSET_ALL_CLR ((uint32_t)0x00000000) /* End of group HDMAxSoftSReqMaskSet */
180 
192 #define INTTCST_CH0 ((uint32_t)0x00000001)
193 #define INTTCST_CH1 ((uint32_t)0x00000002) /* End of group HDMAxIntTcStatus */
198 
209 #define INTTCCLR_CH0 ((uint32_t)0x00000001)
210 #define INTTCCLR_CH1 ((uint32_t)0x00000002)
211 #define INTTCCLR_ALL ((uint32_t)0x00000003) /* End of group HDMAxIntTCClr */
215 
216 
228 #define INTERRST_CH0 ((uint32_t)0x00000001)
229 #define INTERRST_CH1 ((uint32_t)0x00000002) /* End of group HDMAxIntErrStatus */
233 
245 #define INTERRCLR_CH0 ((uint32_t)0x00000001)
246 #define INTERRCLR_CH1 ((uint32_t)0x00000002)
247 #define INTERRCLR_ALL ((uint32_t)0x00000003) /* End of group HDMAxIntErrClr */
251 
263 #define EnabledCH1_TX_CMP ((uint32_t)0x00000000)
264 #define EnabledCH1_TX_RUN ((uint32_t)0x00000002)
265 #define EnabledCH0_TX_CMP ((uint32_t)0x00000000)
266 #define EnabledCH0_TX_RUN ((uint32_t)0x00000001)
267 #define EnabledALL_TX_RUN ((uint32_t)0x00000003) /* End of group HDMAxIntTcClr */
271 
288 #define CH_CFG_MASK_DST_INC ((uint32_t)0xC0000000)
289 #define CH_CFG_MASK_DST_SIZE ((uint32_t)0x30000000)
290 #define CH_CFG_MASK_SRC_INC ((uint32_t)0x0C000000)
291 #define CH_CFG_MASK_SRC_SIZE ((uint32_t)0x03000000)
292 #define CH_CFG_MASK_TRANS_NUM ((uint32_t)0x00003FF0)
293 #define CH_CFG_MASK_CYCLE_CTRL ((uint32_t)0x00000007) /* End of group ChannelCfg */
297  /* End of group HDMA_Private_define */
301 
302 
303 /*------------------------------------------------------------------------------*/
304 /* Enumerated Type Definition */
305 /*------------------------------------------------------------------------------*/
311 /* no define */
312  /* End of group HDMA_Private_define */
316 
317 
318 /*------------------------------------------------------------------------------*/
319 /* Structure Definition */
320 /*------------------------------------------------------------------------------*/
326 /*----------------------------------*/
330 /*----------------------------------*/
331 typedef struct
332 {
333  uint32_t srcEnd;
334  uint32_t dstEnd;
335  uint32_t control;
336  uint32_t reserved;
338  /* End of group HDMA_Private_typedef */
342 
343 
344 /*------------------------------------------------------------------------------*/
345 /* Inline Functions */
346 /*------------------------------------------------------------------------------*/
351 #ifdef DEBUG
352  __STATIC_INLINE int32_t check_param_channel(uint32_t ch);
353 #endif
354 __STATIC_INLINE uint32_t convert_ch_to_reg(uint32_t ch);
355 
356 
357 /*--------------------------------------------------*/
365 /*--------------------------------------------------*/
366 __STATIC_INLINE int32_t check_param_channel(uint32_t ch)
367 {
368  int32_t result = HDMA_PARAM_NG;
369 
370  if (ch <16)
371  {
372  result = HDMA_PARAM_OK;
373  }
374  return (result);
375 }
376 
377 
378 /*--------------------------------------------------*/
385 /*--------------------------------------------------*/
386 __STATIC_INLINE uint32_t convert_ch_to_reg(uint32_t ch)
387 {
388  uint32_t result = (uint32_t)((uint32_t)1 << (uint8_t)ch);
389 
390  return (result);
391 } /* End of group HDMA_Private_functions */
395  /* End of group HDMA */
399  /* End of group Periph_Driver */
403 
404 #ifdef __cplusplus
405 }
406 #endif /* __cplusplus */
407 #endif /* __HDMA_INCLUDE_H */
408 
409 
__STATIC_INLINE uint32_t convert_ch_to_reg(uint32_t ch)
Convert channel to register.
Definition: txz_hdma_include.h:386
Control data structure definition.
Definition: txz_hdma_include.h:331
#define HDMA_PARAM_OK
Definition: txz_hdma_include.h:75
uint32_t control
Definition: txz_hdma_include.h:335
__STATIC_INLINE int32_t check_param_channel(uint32_t ch)
Check the channel no.
Definition: txz_hdma_include.h:366
uint32_t srcEnd
Definition: txz_hdma_include.h:333
All common macro and definition for TXZ peripheral drivers.
#define HDMA_PARAM_NG
Definition: txz_hdma_include.h:76
uint32_t dstEnd
Definition: txz_hdma_include.h:334
uint32_t reserved
Definition: txz_hdma_include.h:336