TMPM4G(1) Group Peripheral Driver User Manual
V1.0.0.0
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I2CxST Macro Definition. | |
#define | I2CxST_NACK ((uint32_t)0x00000008) |
#define | I2CxST_I2CBF ((uint32_t)0x00000004) |
#define | I2CxST_I2CAL ((uint32_t)0x00000002) |
#define | I2CxST_I2C ((uint32_t)0x00000001) |
#define | I2CxST_CLEAR ((uint32_t)0x0000000F) |
I2CxCR1 Macro Definition. | |
#define | I2CxCR1_ACK ((uint32_t)0x00000010) |
#define | I2CxCR1_NOACK ((uint32_t)0x00000008) |
#define | I2CxCR1_BC ((uint32_t)0x000000E0) |
I2CxDBR Macro Definition. | |
#define | I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */ |
I2CxCR2 Macro Definition. | |
#define | I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) |
#define | I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) |
#define | I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) |
#define | I2CxCR2_SWRES_10 ((uint32_t)0x00000002) |
#define | I2CxCR2_SWRES_01 ((uint32_t)0x00000001) |
#define | I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) |
#define | I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) |
#define | I2CxCR2_INIT ((uint32_t)0x00000008) |
I2CxSR Macro Definition. | |
#define | I2CxSR_MST ((uint32_t)0x00000080) |
#define | I2CxSR_TRX ((uint32_t)0x00000040) |
#define | I2CxSR_BB ((uint32_t)0x00000020) |
#define | I2CxSR_PIN ((uint32_t)0x00000010) |
#define | I2CxSR_AL ((uint32_t)0x00000008) |
#define | I2CxSR_AAS ((uint32_t)0x00000004) |
#define | I2CxSR_AD0 ((uint32_t)0x00000002) |
#define | I2CxSR_LRB ((uint32_t)0x00000001) |
I2CxPRS Macro Definition. | |
#define | I2CxPRS_PRCK ((uint32_t)0x0000001F) |
I2CxIE Macro Definition. | |
#define | I2CxIE_SELPINCD ((uint32_t)0x00000040) |
#define | I2CxIE_DMARI2CTX ((uint32_t)0x00000020) |
#define | I2CxIE_DMARI2CRX ((uint32_t)0x00000010) |
#define | I2CxIE_I2C ((uint32_t)0x00000001) |
#define | I2CxIE_CLEAR ((uint32_t)0x00000000) |
I2CxOP Macro Definition. | |
#define | I2CxOP_DISAL ((uint32_t)0x00000080) |
#define | I2CxOP_SA2ST ((uint32_t)0x00000040) |
#define | I2CxOP_SAST ((uint32_t)0x00000020) |
#define | I2CxOP_NFSEL ((uint32_t)0x00000010) |
#define | I2CxOP_RSTA ((uint32_t)0x00000008) |
#define | I2CxOP_GCDI ((uint32_t)0x00000004) |
#define | I2CxOP_SREN ((uint32_t)0x00000002) |
#define | I2CxOP_MFACK ((uint32_t)0x00000001) |
#define | I2CxOP_INIT ((uint32_t)0x00000084) |
#define | I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) |
I2CxAR Macro Definition. | |
#define | I2CxAR_ALS ((uint32_t)0x00000001) |
#define | I2CxAR_INIT ((uint32_t)0x00000000) |
#define | I2CxAR2_INIT ((uint32_t)0x00000000) |
I2CxPM Macro Definition. | |
#define | I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */ |
I2CxWUPCR_INT Macro Definition. | |
#define | I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */ |
#define | I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */ |
I2CxWUPCR_RST Macro Definition. | |
#define | I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */ |
#define | I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */ |
I2CxWUPCR_ACK Macro Definition. | |
#define | I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */ |
#define | I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */ |
#define I2CxAR2_INIT ((uint32_t)0x00000000) |
Initial Settings.
#define I2CxAR_ALS ((uint32_t)0x00000001) |
ALS.
#define I2CxAR_INIT ((uint32_t)0x00000000) |
Initial Settings.
#define I2CxCR1_ACK ((uint32_t)0x00000010) |
ACK
#define I2CxCR1_BC ((uint32_t)0x000000E0) |
BC
#define I2CxCR1_NOACK ((uint32_t)0x00000008) |
NOACK
#define I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) |
I2CM=0
#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) |
I2CM=1
#define I2CxCR2_INIT ((uint32_t)0x00000008) |
MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00
#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) |
PIN=1
#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) |
MST=1,TRX=1,BB=1,PIN=1,I2CM=1
#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) |
MST=1,TRX=1,BB=0,PIN=1,I2CM=1
#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) |
SWRES=01
#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) |
SWRES=10
#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */ |
#define I2CxIE_CLEAR ((uint32_t)0x00000000) |
All Clear Setting
#define I2CxIE_DMARI2CRX ((uint32_t)0x00000010) |
DMARI2CRX
#define I2CxIE_DMARI2CTX ((uint32_t)0x00000020) |
DMARI2CTX
#define I2CxIE_I2C ((uint32_t)0x00000001) |
INTI2C
#define I2CxIE_SELPINCD ((uint32_t)0x00000040) |
SELPINCD
#define I2CxOP_DISAL ((uint32_t)0x00000080) |
DISAL
#define I2CxOP_GCDI ((uint32_t)0x00000004) |
GDDI
#define I2CxOP_INIT ((uint32_t)0x00000084) |
Initial Settings.
#define I2CxOP_MFACK ((uint32_t)0x00000001) |
MFACK
#define I2CxOP_NFSEL ((uint32_t)0x00000010) |
NFSEL
#define I2CxOP_RSTA ((uint32_t)0x00000008) |
RSTA
#define I2CxOP_SA2ST ((uint32_t)0x00000040) |
SA2ST
#define I2CxOP_SAST ((uint32_t)0x00000020) |
SAST
#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) |
Slave Initial Settings.
#define I2CxOP_SREN ((uint32_t)0x00000002) |
SREN
#define I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */ |
#define I2CxPRS_PRCK ((uint32_t)0x0000001F) |
PRCK
#define I2CxSR_AAS ((uint32_t)0x00000004) |
AAS
#define I2CxSR_AD0 ((uint32_t)0x00000002) |
AD0
#define I2CxSR_AL ((uint32_t)0x00000008) |
AL
#define I2CxSR_BB ((uint32_t)0x00000020) |
BB
#define I2CxSR_LRB ((uint32_t)0x00000001) |
LRB
#define I2CxSR_MST ((uint32_t)0x00000080) |
MST
#define I2CxSR_PIN ((uint32_t)0x00000010) |
PIN
#define I2CxSR_TRX ((uint32_t)0x00000040) |
TRX
#define I2CxST_CLEAR ((uint32_t)0x0000000F) |
All Bits Clear.
#define I2CxST_I2C ((uint32_t)0x00000001) |
I2C Interrupt Status.
#define I2CxST_I2CAL ((uint32_t)0x00000002) |
I2CAL Interrupt Status.
#define I2CxST_I2CBF ((uint32_t)0x00000004) |
I2CBF Interrupt Status.
#define I2CxST_NACK ((uint32_t)0x00000008) |
NACK Interrupt Status.
#define I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */ |
#define I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */ |
#define I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */ |
#define I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */ |
#define I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */ |
#define I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */ |