66 #define HDMA_CH_NUM ((uint32_t)2) 76 #define HDMA_TRANS_TYPE_SINGLE ((uint32_t)0x00000000) 77 #define HDMA_TRANS_TYPE_BURST ((uint32_t)0x00000001) 87 #define HDMA_SRC_REQ_CH_MEM_USE ((uint32_t)0x00000000) 88 #define HDMA_SRC_REQ_CH_1 ((uint32_t)0x00000001) 89 #define HDMA_SRC_REQ_CH_2 ((uint32_t)0x00000002) 90 #define HDMA_SRC_REQ_CH_3 ((uint32_t)0x00000003) 91 #define HDMA_SRC_REQ_CH_4 ((uint32_t)0x00000004) 92 #define HDMA_SRC_REQ_CH_5 ((uint32_t)0x00000005) 93 #define HDMA_SRC_REQ_CH_6 ((uint32_t)0x00000006) 94 #define HDMA_SRC_REQ_CH_7 ((uint32_t)0x00000007) 95 #define HDMA_SRC_REQ_CH_8 ((uint32_t)0x00000008) 96 #define HDMA_SRC_REQ_CH_9 ((uint32_t)0x00000009) 97 #define HDMA_SRC_REQ_CH_10 ((uint32_t)0x0000000A) 98 #define HDMA_SRC_REQ_CH_11 ((uint32_t)0x0000000B) 99 #define HDMA_SRC_REQ_CH_12 ((uint32_t)0x0000000C) 100 #define HDMA_SRC_REQ_CH_13 ((uint32_t)0x0000000D) 101 #define HDMA_SRC_REQ_CH_14 ((uint32_t)0x0000000E) 102 #define HDMA_SRC_REQ_CH_15 ((uint32_t)0x0000000F) 112 #define HDMA_DST_REQ_CH_MEM_USE ((uint32_t)0x00000000) 113 #define HDMA_DST_REQ_CH_1 ((uint32_t)0x00000001) 114 #define HDMA_DST_REQ_CH_2 ((uint32_t)0x00000002) 115 #define HDMA_DST_REQ_CH_3 ((uint32_t)0x00000003) 116 #define HDMA_DST_REQ_CH_4 ((uint32_t)0x00000004) 117 #define HDMA_DST_REQ_CH_5 ((uint32_t)0x00000005) 118 #define HDMA_DST_REQ_CH_6 ((uint32_t)0x00000006) 119 #define HDMA_DST_REQ_CH_7 ((uint32_t)0x00000007) 120 #define HDMA_DST_REQ_CH_8 ((uint32_t)0x00000008) 121 #define HDMA_DST_REQ_CH_9 ((uint32_t)0x00000009) 122 #define HDMA_DST_REQ_CH_10 ((uint32_t)0x0000000A) 123 #define HDMA_DST_REQ_CH_11 ((uint32_t)0x0000000B) 124 #define HDMA_DST_REQ_CH_12 ((uint32_t)0x0000000C) 125 #define HDMA_DST_REQ_CH_13 ((uint32_t)0x0000000D) 126 #define HDMA_DST_REQ_CH_14 ((uint32_t)0x0000000E) 127 #define HDMA_DST_REQ_CH_15 ((uint32_t)0x0000000F) 137 #define HDMA_TRANS_INT_COMP_DISABLE ((uint32_t)0x00000000) 138 #define HDMA_TRANS_INT_COMP_ENABLE ((uint32_t)0x80000000) 149 #define HDMA_LLI_ADDRESS_MIN ((uint32_t)0x00000000) 150 #define HDMA_LLI_ADDRESS_MAX ((uint32_t)0x3FFFFFFF) 161 #define HDMA_TRANS_NUM_RANGE_MIN ((uint32_t)0x00000001) 162 #define HDMA_TRANS_NUM_RANGE_MAX ((uint32_t)0x00000400) 172 #define HDMA_DST_ADDR_FIX ((uint32_t)0x00000000) 173 #define HDMA_DST_ADDR_INC ((uint32_t)0x08000000) 183 #define HDMA_SRC_ADDR_FIX ((uint32_t)0x00000000) 184 #define HDMA_SRC_ADDR_INC ((uint32_t)0x04000000) 194 #define HDMA_DST_BITWIDTH_1BYTE ((uint32_t)0x00000000) 195 #define HDMA_DST_BITWIDTH_2BYTE ((uint32_t)0x00200000) 196 #define HDMA_DST_BITWIDTH_4BYTE ((uint32_t)0x00400000) 206 #define HDMA_DST_BURSTSIZE_1BEAT ((uint32_t)0x00000000) 207 #define HDMA_DST_BURSTSIZE_4BEAT ((uint32_t)0x00008000) 208 #define HDMA_DST_BURSTSIZE_8BEAT ((uint32_t)0x00010000) 209 #define HDMA_DST_BURSTSIZE_16BEAT ((uint32_t)0x00018000) 210 #define HDMA_DST_BURSTSIZE_32BEAT ((uint32_t)0x00020000) 211 #define HDMA_DST_BURSTSIZE_64BEAT ((uint32_t)0x00028000) 212 #define HDMA_DST_BURSTSIZE_128BEAT ((uint32_t)0x00030000) 213 #define HDMA_DST_BURSTSIZE_256BEAT ((uint32_t)0x00038000) 223 #define HDMA_SRC_BITWIDTH_1BYTE ((uint32_t)0x00000000) 224 #define HDMA_SRC_BITWIDTH_2BYTE ((uint32_t)0x00040000) 225 #define HDMA_SRC_BITWIDTH_4BYTE ((uint32_t)0x00080000) 235 #define HDMA_SRC_BURSTSIZE_1BEAT ((uint32_t)0x00000000) 236 #define HDMA_SRC_BURSTSIZE_4BEAT ((uint32_t)0x00001000) 237 #define HDMA_SRC_BURSTSIZE_8BEAT ((uint32_t)0x00002000) 238 #define HDMA_SRC_BURSTSIZE_16BEAT ((uint32_t)0x00003000) 239 #define HDMA_SRC_BURSTSIZE_32BEAT ((uint32_t)0x00004000) 240 #define HDMA_SRC_BURSTSIZE_64BEAT ((uint32_t)0x00005000) 241 #define HDMA_SRC_BURSTSIZE_128BEAT ((uint32_t)0x00006000) 242 #define HDMA_SRC_BURSTSIZE_256BEAT ((uint32_t)0x00007000) 273 #define HDMA_CH_E_DISABLE ((uint32_t)0x00000000) 274 #define HDMA_CH_E_ENABLE ((uint32_t)0x00000001) 284 #define HDMA_CH_SRCPERI_MASK ((uint32_t)0x0000001E) 294 #define HDMA_CH_FLOWCNT_MEM_MEM ((uint32_t)0x00000000) 295 #define HDMA_CH_FLOWCNT_MEM_PERI ((uint32_t)0x00000800) 296 #define HDMA_CH_FLOWCNT_PERI_MEM ((uint32_t)0x00001000) 297 #define HDMA_CH_FLOWCNT_PERI_PERI ((uint32_t)0x00001800) 298 #define HDMA_CH_FLOWCNT_MASK ((uint32_t)0x00001800) 308 #define HDMA_CH_DSTPERI_MASK ((uint32_t)0x000003C0) 318 #define HDMA_CH_IE_DISABLE ((uint32_t)0x00000000) 319 #define HDMA_CH_IE_ENABLE ((uint32_t)0x00004000) 329 #define HDMA_CH_ITC_DISABLE ((uint32_t)0x00000000) 330 #define HDMA_CH_ITC_ENABLE ((uint32_t)0x00008000) 340 #define HDMA_CH_LOCK_DISABLE ((uint32_t)0x00000000) 341 #define HDMA_CH_LOCK_ENABLE ((uint32_t)0x00010000) 351 #define HDMA_CH_ACT_MASK ((uint32_t)0x00020000) 362 #define HDMA_CH_HALT_ENABLE ((uint32_t)0x00000000) 363 #define HDMA_CH_HALT_DISABLE ((uint32_t)0x00040000) 376 #define HDMA_ITC_DISABLE ((uint32_t)0x00000000) 377 #define HDMA_ITC_ENABLE ((uint32_t)0x80000000) uint32_t dstInc
Definition: txz_hdma.h:427
uint32_t e
Definition: txz_hdma.h:463
uint32_t lock
Definition: txz_hdma.h:455
TXZ_Result hdma_error_irq_handler(hdma_t *p_obj)
TXZ_Result hdma_IE_enable(hdma_t *p_obj, uint32_t dma_ch)
uint32_t dstAdd
Definition: txz_hdma.h:417
TXZ_Result hdma_ITC_enable(hdma_t *p_obj, uint32_t dma_ch)
TXZ_Result hdma_ITC_disable(hdma_t *p_obj, uint32_t dma_ch)
Initial setting structure definition.
Definition: txz_hdma.h:414
uint32_t transsize
Definition: txz_hdma.h:439
TXZ_Result
Definition: txz_driver_def.h:43
uint32_t dstReqCh
Definition: txz_hdma.h:478
uint32_t srcInc
Definition: txz_hdma.h:433
TXZ_Result hdma_lli_set(hdma_t *p_obj, uint32_t dma_ch)
TXZ_Result get_src_address(hdma_t *p_obj, uint32_t dma_ch, uint32_t *addr)
TXZ_Result hdma_FlowType_Set(hdma_t *p_obj, uint32_t dma_ch, uint32_t type)
Channel setting structure definition.
Definition: txz_hdma.h:472
TXZ_Result hdma_IE_disable(hdma_t *p_obj, uint32_t dma_ch)
TSB_DMAC_TypeDef * p_instance
Definition: txz_hdma.h:492
Channel control setting structure definition.
Definition: txz_hdma.h:425
uint32_t dstSize
Definition: txz_hdma.h:429
uint32_t itc
Definition: txz_hdma.h:457
TXZ_Result hdma_stopIt(hdma_t *p_obj, uint32_t dma_ch)
TXZ_Result hdma_irq_handler(hdma_t *p_obj)
uint32_t flowCnt
Definition: txz_hdma.h:461
TXZ_Result hdma_deinit(hdma_t *p_obj)
hdma_ch_cnt_t cnt
Definition: txz_hdma.h:479
TXZ_Result hdma_channel_init(hdma_t *p_obj, uint32_t dma_ch)
hdma_initial_setting_t init
Definition: txz_hdma.h:493
uint32_t dstBurstSize
Definition: txz_hdma.h:431
HDMA handle structure definition.
Definition: txz_hdma.h:490
TXZ_Result hdma_srcPeri_Set(hdma_t *p_obj, uint32_t dma_ch)
TXZ_Result hdma_startIt(hdma_t *p_obj, uint32_t dma_ch)
All common macro and definition for TXZ peripheral drivers.
#define HDMA_CH_NUM
Definition: txz_hdma.h:66
uint32_t halt
Definition: txz_hdma.h:453
TXZ_Result hdma_startPeriIt(hdma_t *p_obj, uint32_t dma_ch)
struct hdma_handle hdma_t
HDMA handle structure definition.
TXZ_Result hdma_E_disable(hdma_t *p_obj, uint32_t dma_ch)
Channel config setting structure definition.
Definition: txz_hdma.h:451
TXZ_Result hdma_get_error(hdma_t *p_obj, uint32_t *p_err)
TXZ_Result hdma_LOCK_disable(hdma_t *p_obj, uint32_t dma_ch)
uint32_t srcReqCh
Definition: txz_hdma.h:477
TXZ_Result hdma_HALT_enable(hdma_t *p_obj, uint32_t dma_ch)
hdma_ch_cfg_t cfg
Definition: txz_hdma.h:481
uint32_t lli
Definition: txz_hdma.h:441
TXZ_Result get_dst_address(hdma_t *p_obj, uint32_t dma_ch, uint32_t *addr)
TXZ_Result hdma_E_enable(hdma_t *p_obj, uint32_t dma_ch)
uint32_t id
Definition: txz_hdma.h:475
uint32_t srcBurstSize
Definition: txz_hdma.h:437
uint32_t type
Definition: txz_hdma.h:476
TXZ_Result hdma_init(hdma_t *p_obj)
TXZ_Result hdma_stopPeriIt(hdma_t *p_obj, uint32_t dma_ch)
uint32_t srcAdd
Definition: txz_hdma.h:416
TXZ_Result hdma_LOCK_enable(hdma_t *p_obj, uint32_t dma_ch)
TXZ_Result hdma_clear_error(hdma_t *p_obj)
TXZ_Result hdma_dstPeri_Set(hdma_t *p_obj, uint32_t dma_ch)
uint32_t srcSize
Definition: txz_hdma.h:435
uint32_t ie
Definition: txz_hdma.h:459
hdma_ch_setting_t ch[HDMA_CH_NUM]
Definition: txz_hdma.h:494