#include <TMPM4G6.h>
§ AREASEL
Flash Area Selection Register
§ BNKCR
Flash Bank Change Register
§ BUFDISCLR
Flash Buffer Disable and Clear Register
§ CR
§ KCR
§ PMR0
Flash Protect Mask Register 0
§ PMR1
Flash Protect Mask Register 1
§ PMR3
Flash Protect Mask Register 3
§ PMR4
Flash Protect Mask Register 4
§ PMR6
Flash Protect Mask Register 6
§ PSR0
Flash Protect Status Register 0
§ PSR1
Flash Protect Status Register 1
§ PSR3
Flash Protect Status Register 3
§ PSR4
Flash Protect Status Register 4
§ PSR6
Flash Protect Status Register 6
§ RESERVED0
§ RESERVED1
§ RESERVED10
§ RESERVED11
§ RESERVED2
§ RESERVED3
§ RESERVED4
§ RESERVED5
§ RESERVED6
§ RESERVED7
§ RESERVED8
§ RESERVED9
§ SBMR
Flash Security Bit Mask Register
§ SR0
§ SR1
§ SSR
Flash Security Status Register
§ STSCLR
Flash Status Clear Register
§ SWPSR
Flash Memory SWP Status Register
The documentation for this struct was generated from the following files:
- C:/W_JOB(TOSHIBA)/TMPM4G9/release/TMPM4G9_release_20190424/TMPM4G9_V1000/Libraries/CMSIS/TMPM4G6.h
- C:/W_JOB(TOSHIBA)/TMPM4G9/release/TMPM4G9_release_20190424/TMPM4G9_V1000/Libraries/CMSIS/TMPM4G7.h
- C:/W_JOB(TOSHIBA)/TMPM4G9/release/TMPM4G9_release_20190424/TMPM4G9_V1000/Libraries/CMSIS/TMPM4G8.h
- C:/W_JOB(TOSHIBA)/TMPM4G9/release/TMPM4G9_release_20190424/TMPM4G9_V1000/Libraries/CMSIS/TMPM4G9.h