26 #include "txz_sample_def.h" 86 #define REG_DNF_NFCKCR_NFCKS_STOP ((uint32_t)0x00000000) 87 #define REG_DNF_NFCKCR_NFCKS_CLOCK_2 ((uint32_t)0x00000001) 88 #define REG_DNF_NFCKCR_NFCKS_CLOCK_4 ((uint32_t)0x00000002) 89 #define REG_DNF_NFCKCR_NFCKS_CLOCK_8 ((uint32_t)0x00000003) 90 #define REG_DNF_NFCKCR_NFCKS_CLOCK_16 ((uint32_t)0x00000004) 91 #define REG_DNF_NFCKCR_NFCKS_CLOCK_32 ((uint32_t)0x00000005) 92 #define REG_DNF_NFCKCR_NFCKS_CLOCK_64 ((uint32_t)0x00000006) 93 #define REG_DNF_NFCKCR_NFCKS_CLOCK_128 ((uint32_t)0x00000007) 114 #define REG_DNF_NFENCR_NFEN10_MASK ((uint32_t)0x00000400) 115 #define REG_DNF_NFENCR_NFEN10_DISABLE ((uint32_t)0x00000000) 116 #define REG_DNF_NFENCR_NFEN10_ENABLE ((uint32_t)0x00000400) 126 #define REG_DNF_NFENCR_NFEN9_MASK ((uint32_t)0x00000200) 127 #define REG_DNF_NFENCR_NFEN9_DISABLE ((uint32_t)0x00000000) 128 #define REG_DNF_NFENCR_NFEN9_ENABLE ((uint32_t)0x00000200) 138 #define REG_DNF_NFENCR_NFEN8_MASK ((uint32_t)0x00000100) 139 #define REG_DNF_NFENCR_NFEN8_DISABLE ((uint32_t)0x00000000) 140 #define REG_DNF_NFENCR_NFEN8_ENABLE ((uint32_t)0x00000100) 150 #define REG_DNF_NFENCR_NFEN7_MASK ((uint32_t)0x00000080) 151 #define REG_DNF_NFENCR_NFEN7_DISABLE ((uint32_t)0x00000000) 152 #define REG_DNF_NFENCR_NFEN7_ENABLE ((uint32_t)0x00000080) 162 #define REG_DNF_NFENCR_NFEN6_MASK ((uint32_t)0x00000040) 163 #define REG_DNF_NFENCR_NFEN6_DISABLE ((uint32_t)0x00000000) 164 #define REG_DNF_NFENCR_NFEN6_ENABLE ((uint32_t)0x00000040) 174 #define REG_DNF_NFENCR_NFEN5_MASK ((uint32_t)0x00000020) 175 #define REG_DNF_NFENCR_NFEN5_DISABLE ((uint32_t)0x00000000) 176 #define REG_DNF_NFENCR_NFEN5_ENABLE ((uint32_t)0x00000020) 186 #define REG_DNF_NFENCR_NFEN4_MASK ((uint32_t)0x00000010) 187 #define REG_DNF_NFENCR_NFEN4_DISABLE ((uint32_t)0x00000000) 188 #define REG_DNF_NFENCR_NFEN4_ENABLE ((uint32_t)0x00000010) 198 #define REG_DNF_NFENCR_NFEN3_MASK ((uint32_t)0x00000008) 199 #define REG_DNF_NFENCR_NFEN3_DISABLE ((uint32_t)0x00000000) 200 #define REG_DNF_NFENCR_NFEN3_ENABLE ((uint32_t)0x00000008) 210 #define REG_DNF_NFENCR_NFEN2_MASK ((uint32_t)0x00000004) 211 #define REG_DNF_NFENCR_NFEN2_DISABLE ((uint32_t)0x00000000) 212 #define REG_DNF_NFENCR_NFEN2_ENABLE ((uint32_t)0x00000004) 222 #define REG_DNF_NFENCR_NFEN1_MASK ((uint32_t)0x00000002) 223 #define REG_DNF_NFENCR_NFEN1_DISABLE ((uint32_t)0x00000000) 224 #define REG_DNF_NFENCR_NFEN1_ENABLE ((uint32_t)0x00000002) 234 #define REG_DNF_NFENCR_NFEN0_MASK ((uint32_t)0x00000001) 235 #define REG_DNF_NFENCR_NFEN0_DISABLE ((uint32_t)0x00000000) 236 #define REG_DNF_NFENCR_NFEN0_ENABLE ((uint32_t)0x00000001) void REG_DNFENCR_disable(TSB_DNF_TypeDef *p_reg, uint32_t bit)
Set Interrupt Noise Filter Control.
Definition: dnf.c:388
void REG_DNFCKCR_set(TSB_DNF_TypeDef *p_reg, uint32_t clock)
Set Value Noise Filter Clock Select.
Definition: dnf.c:249
uint32_t REG_DNFENCR_get(TSB_DNF_TypeDef *p_reg)
Get the Interrupt Noise Filter Control.
Definition: dnf.c:434
DNF.
Definition: TMPM4G6.h:621
Input control structure definition.
Definition: dnf.h:276
uint32_t nfcks
Definition: dnf.h:277
void REG_DNFENCR_enable(TSB_DNF_TypeDef *p_reg, uint32_t bit)
Set Interrupt Noise Filter Control.
Definition: dnf.c:329
uint32_t REG_DNFCKCR_get(TSB_DNF_TypeDef *p_reg)
Get value Noise Filter Clock Select.
Definition: dnf.c:277
uint32_t nfencr
Definition: dnf.h:279