TMPM4G9  V1.0.0.0

ARM Prime Cell PL011. More...

#include <TMPM4G6.h>

Data Fields

__IO uint32_t DR
 
union {
   __I uint32_t   RSR
 
   __O uint32_t   ECR
 
}; 
 
uint32_t RESERVED0 [4]
 
__I uint32_t FR
 
uint32_t RESERVED1
 
__IO uint32_t ILPR
 
__IO uint32_t BRD
 
__IO uint32_t FBRD
 
__IO uint32_t LCR_H
 
__IO uint32_t CR
 
__IO uint32_t IFLS
 
__IO uint32_t IMSC
 
__I uint32_t RIS
 
__I uint32_t MIS
 
__O uint32_t ICR
 
__IO uint32_t DMACR
 
union {
   __I uint32_t   RSR
 
   __O uint32_t   ECR
 
}; 
 
union {
   __I uint32_t   RSR
 
   __O uint32_t   ECR
 
}; 
 
union {
   __I uint32_t   RSR
 
   __O uint32_t   ECR
 
}; 
 

Detailed Description

ARM Prime Cell PL011.

Field Documentation

§ @1

union { ... }

§ @13

union { ... }

§ @5

union { ... }

§ @9

union { ... }

§ BRD

__IO uint32_t BRD

Integer Baud Rate Register

§ CR

__IO uint32_t CR

Cntrol Register

§ DMACR

__IO uint32_t DMACR

DMA Control Register

§ DR

__IO uint32_t DR

Data Register

§ ECR

__O uint32_t ECR

Error Clear Register

§ FBRD

__IO uint32_t FBRD

Fractional Baud Rate Register

§ FR

__I uint32_t FR

Flag Register

§ ICR

__O uint32_t ICR

Interrupt Clear Register

§ IFLS

__IO uint32_t IFLS

Interrupt FIFO Level Select Register

§ ILPR

__IO uint32_t ILPR

IrDA Low-power Counter register

§ IMSC

__IO uint32_t IMSC

Interrupt Mask set/Clear Register

§ LCR_H

__IO uint32_t LCR_H

Line Control Register

§ MIS

__I uint32_t MIS

Masked Interrupt Status Register

§ RESERVED0

uint32_t RESERVED0

§ RESERVED1

uint32_t RESERVED1

§ RIS

__I uint32_t RIS

Raw Interrupt Status Register

§ RSR

__I uint32_t RSR

Receive Status Register


The documentation for this struct was generated from the following files: