TMPM4G9  V1.0.0.0

fsys PLL Select Register. More...

Macros

#define CGPLL0SEL_PLL0ST_MASK   ((uint32_t)0x00000004)
 
#define CGPLL0SEL_PLL0ST_R_FOSC   ((uint32_t)0x00000000)
 
#define CGPLL0SEL_PLL0ST_R_FPLL   ((uint32_t)0x00000004)
 
#define CGPLL0SEL_PLL0SEL_MASK   ((uint32_t)0x00000002)
 
#define CGPLL0SEL_PLL0SEL_RW_FOSC   ((uint32_t)0x00000000)
 
#define CGPLL0SEL_PLL0SEL_RW_FPLL   ((uint32_t)0x00000002)
 
#define CGPLL0SEL_PLL0ON_MASK   ((uint32_t)0x00000001)
 
#define CGPLL0SEL_PLL0ON_RW_DISABLE   ((uint32_t)0x00000000)
 
#define CGPLL0SEL_PLL0ON_RW_ENABLE   ((uint32_t)0x00000001)
 
#define CGPLL0SEL_PLL0ST_MASK   ((uint32_t)0x00000004)
 
#define CGPLL0SEL_PLL0ST_R_FOSC   ((uint32_t)0x00000000)
 
#define CGPLL0SEL_PLL0ST_R_FPLL   ((uint32_t)0x00000004)
 
#define CGPLL0SEL_PLL0SEL_MASK   ((uint32_t)0x00000002)
 
#define CGPLL0SEL_PLL0SEL_RW_FOSC   ((uint32_t)0x00000000)
 
#define CGPLL0SEL_PLL0SEL_RW_FPLL   ((uint32_t)0x00000002)
 
#define CGPLL0SEL_PLL0ON_MASK   ((uint32_t)0x00000001)
 
#define CGPLL0SEL_PLL0ON_RW_DISABLE   ((uint32_t)0x00000000)
 
#define CGPLL0SEL_PLL0ON_RW_ENABLE   ((uint32_t)0x00000001)
 

Detailed Description

fsys PLL Select Register.

Detail.

Bit Bit Symbol
31:8 PLL0SET
7:3 -
2 PLL0ST
1 PLL0SEL
0 PLL0ON

Macro Definition Documentation

§ CGPLL0SEL_PLL0ON_MASK [1/2]

#define CGPLL0SEL_PLL0ON_MASK   ((uint32_t)0x00000001)

PLL0ON :Mask.

§ CGPLL0SEL_PLL0ON_MASK [2/2]

#define CGPLL0SEL_PLL0ON_MASK   ((uint32_t)0x00000001)

PLL0ON :Mask.

§ CGPLL0SEL_PLL0ON_RW_DISABLE [1/2]

#define CGPLL0SEL_PLL0ON_RW_DISABLE   ((uint32_t)0x00000000)

PLL0ON :[R/W] :Disable

§ CGPLL0SEL_PLL0ON_RW_DISABLE [2/2]

#define CGPLL0SEL_PLL0ON_RW_DISABLE   ((uint32_t)0x00000000)

PLL0ON :[R/W] :Disable

§ CGPLL0SEL_PLL0ON_RW_ENABLE [1/2]

#define CGPLL0SEL_PLL0ON_RW_ENABLE   ((uint32_t)0x00000001)

PLL0ON :[R/W] :Enable

§ CGPLL0SEL_PLL0ON_RW_ENABLE [2/2]

#define CGPLL0SEL_PLL0ON_RW_ENABLE   ((uint32_t)0x00000001)

PLL0ON :[R/W] :Enable

§ CGPLL0SEL_PLL0SEL_MASK [1/2]

#define CGPLL0SEL_PLL0SEL_MASK   ((uint32_t)0x00000002)

PLL0SEL :Mask.

§ CGPLL0SEL_PLL0SEL_MASK [2/2]

#define CGPLL0SEL_PLL0SEL_MASK   ((uint32_t)0x00000002)

PLL0SEL :Mask.

§ CGPLL0SEL_PLL0SEL_RW_FOSC [1/2]

#define CGPLL0SEL_PLL0SEL_RW_FOSC   ((uint32_t)0x00000000)

PLL0SEL :[R/W] :fosc

§ CGPLL0SEL_PLL0SEL_RW_FOSC [2/2]

#define CGPLL0SEL_PLL0SEL_RW_FOSC   ((uint32_t)0x00000000)

PLL0SEL :[R/W] :fosc

§ CGPLL0SEL_PLL0SEL_RW_FPLL [1/2]

#define CGPLL0SEL_PLL0SEL_RW_FPLL   ((uint32_t)0x00000002)

PLL0SEL :[R/W] :fpll

§ CGPLL0SEL_PLL0SEL_RW_FPLL [2/2]

#define CGPLL0SEL_PLL0SEL_RW_FPLL   ((uint32_t)0x00000002)

PLL0SEL :[R/W] :fpll

§ CGPLL0SEL_PLL0ST_MASK [1/2]

#define CGPLL0SEL_PLL0ST_MASK   ((uint32_t)0x00000004)

PLL0ST :Mask.

§ CGPLL0SEL_PLL0ST_MASK [2/2]

#define CGPLL0SEL_PLL0ST_MASK   ((uint32_t)0x00000004)

PLL0ST :Mask.

§ CGPLL0SEL_PLL0ST_R_FOSC [1/2]

#define CGPLL0SEL_PLL0ST_R_FOSC   ((uint32_t)0x00000000)

PLL0ST :[R] :fosc

§ CGPLL0SEL_PLL0ST_R_FOSC [2/2]

#define CGPLL0SEL_PLL0ST_R_FOSC   ((uint32_t)0x00000000)

PLL0ST :[R] :fosc

§ CGPLL0SEL_PLL0ST_R_FPLL [1/2]

#define CGPLL0SEL_PLL0ST_R_FPLL   ((uint32_t)0x00000004)

PLL0ST :[R] :fpll

§ CGPLL0SEL_PLL0ST_R_FPLL [2/2]

#define CGPLL0SEL_PLL0ST_R_FPLL   ((uint32_t)0x00000004)

PLL0ST :[R] :fpll