TMPM4G(1) Group Peripheral Driver User Manual  V1.0.0.0
UTILITIES_Private_define

I2CxST Macro Definition.

I2CxST Register Macro Definition.

#define I2CxST_NACK   ((uint32_t)0x00000008)
 
#define I2CxST_I2CBF   ((uint32_t)0x00000004)
 
#define I2CxST_I2CAL   ((uint32_t)0x00000002)
 
#define I2CxST_I2C   ((uint32_t)0x00000001)
 
#define I2CxST_CLEAR   ((uint32_t)0x0000000F)
 

I2CxCR1 Macro Definition.

I2CxCR1 Register Macro Definition.

#define I2CxCR1_ACK   ((uint32_t)0x00000010)
 
#define I2CxCR1_NOACK   ((uint32_t)0x00000008)
 
#define I2CxCR1_BC   ((uint32_t)0x000000E0)
 

I2CxDBR Macro Definition.

I2CxDBR Register Macro Definition.

#define I2CxDBR_DB_MASK   ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */
 

I2CxCR2 Macro Definition.

I2CxCR2 Register Macro Definition.

#define I2CxCR2_PIN_CLEAR   ((uint32_t)0x00000010)
 
#define I2CxCR2_I2CM_DISABLE   ((uint32_t)0x00000000)
 
#define I2CxCR2_I2CM_ENABLE   ((uint32_t)0x00000008)
 
#define I2CxCR2_SWRES_10   ((uint32_t)0x00000002)
 
#define I2CxCR2_SWRES_01   ((uint32_t)0x00000001)
 
#define I2CxCR2_START_CONDITION   ((uint32_t)0x000000F8)
 
#define I2CxCR2_STOP_CONDITION   ((uint32_t)0x000000D8)
 
#define I2CxCR2_INIT   ((uint32_t)0x00000008)
 

I2CxSR Macro Definition.

I2CxSR Register Macro Definition.

#define I2CxSR_MST   ((uint32_t)0x00000080)
 
#define I2CxSR_TRX   ((uint32_t)0x00000040)
 
#define I2CxSR_BB   ((uint32_t)0x00000020)
 
#define I2CxSR_PIN   ((uint32_t)0x00000010)
 
#define I2CxSR_AL   ((uint32_t)0x00000008)
 
#define I2CxSR_AAS   ((uint32_t)0x00000004)
 
#define I2CxSR_AD0   ((uint32_t)0x00000002)
 
#define I2CxSR_LRB   ((uint32_t)0x00000001)
 

I2CxPRS Macro Definition.

I2CxPRS Register Macro Definition.

#define I2CxPRS_PRCK   ((uint32_t)0x0000001F)
 

I2CxIE Macro Definition.

I2CxIE Register Macro Definition.

#define I2CxIE_SELPINCD   ((uint32_t)0x00000040)
 
#define I2CxIE_DMARI2CTX   ((uint32_t)0x00000020)
 
#define I2CxIE_DMARI2CRX   ((uint32_t)0x00000010)
 
#define I2CxIE_I2C   ((uint32_t)0x00000001)
 
#define I2CxIE_CLEAR   ((uint32_t)0x00000000)
 

I2CxOP Macro Definition.

I2CxOP Register Macro Definition.

#define I2CxOP_DISAL   ((uint32_t)0x00000080)
 
#define I2CxOP_SA2ST   ((uint32_t)0x00000040)
 
#define I2CxOP_SAST   ((uint32_t)0x00000020)
 
#define I2CxOP_NFSEL   ((uint32_t)0x00000010)
 
#define I2CxOP_RSTA   ((uint32_t)0x00000008)
 
#define I2CxOP_GCDI   ((uint32_t)0x00000004)
 
#define I2CxOP_SREN   ((uint32_t)0x00000002)
 
#define I2CxOP_MFACK   ((uint32_t)0x00000001)
 
#define I2CxOP_INIT   ((uint32_t)0x00000084)
 
#define I2CxOP_SLAVE_INIT   ((uint32_t)0x00000084)
 

I2CxAR Macro Definition.

I2CxAR Register Macro Definition.

#define I2CxAR_ALS   ((uint32_t)0x00000001)
 
#define I2CxAR_INIT   ((uint32_t)0x00000000)
 
#define I2CxAR2_INIT   ((uint32_t)0x00000000)
 

I2CxPM Macro Definition.

I2CxPM Register Macro Definition.

#define I2CxPM_SDA_SCL   ((uint32_t)0x00000003) /* SDA and SCL level. */
 

I2CxWUPCR_INT Macro Definition.

I2CxWUPCR_INT Register Macro Definition.

#define I2CxWUPCR_INT_RELESE   ((uint32_t)0x00000001) /* Interrupt Release. */
 
#define I2CxWUPCR_INT_HOLD   ((uint32_t)0x00000000) /* Interrupt setting keep it. */
 

I2CxWUPCR_RST Macro Definition.

I2CxWUPCR_RST Register Macro Definition.

#define I2CxWUPCR_RST_RESET   ((uint32_t)0x00000010) /* I2C BUS Reset. */
 
#define I2CxWUPCR_RST_RELEASE   ((uint32_t)0x00000000) /* I2C BUS Reset Release. */
 

I2CxWUPCR_ACK Macro Definition.

I2CxWUPCR_ACK Register Macro Definition.

#define I2CxWUPCR_ACK   ((uint32_t)0x00000020) /* ACK Output. Output "0" */
 
#define I2CxWUPCR_NACK   ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */
 

Detailed Description

Macro Definition Documentation

§ I2CxAR2_INIT

#define I2CxAR2_INIT   ((uint32_t)0x00000000)

Initial Settings.

§ I2CxAR_ALS

#define I2CxAR_ALS   ((uint32_t)0x00000001)

ALS.

§ I2CxAR_INIT

#define I2CxAR_INIT   ((uint32_t)0x00000000)

Initial Settings.

§ I2CxCR1_ACK

#define I2CxCR1_ACK   ((uint32_t)0x00000010)

ACK

§ I2CxCR1_BC

#define I2CxCR1_BC   ((uint32_t)0x000000E0)

BC

§ I2CxCR1_NOACK

#define I2CxCR1_NOACK   ((uint32_t)0x00000008)

NOACK

§ I2CxCR2_I2CM_DISABLE

#define I2CxCR2_I2CM_DISABLE   ((uint32_t)0x00000000)

I2CM=0

§ I2CxCR2_I2CM_ENABLE

#define I2CxCR2_I2CM_ENABLE   ((uint32_t)0x00000008)

I2CM=1

§ I2CxCR2_INIT

#define I2CxCR2_INIT   ((uint32_t)0x00000008)

MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00

§ I2CxCR2_PIN_CLEAR

#define I2CxCR2_PIN_CLEAR   ((uint32_t)0x00000010)

PIN=1

§ I2CxCR2_START_CONDITION

#define I2CxCR2_START_CONDITION   ((uint32_t)0x000000F8)

MST=1,TRX=1,BB=1,PIN=1,I2CM=1

§ I2CxCR2_STOP_CONDITION

#define I2CxCR2_STOP_CONDITION   ((uint32_t)0x000000D8)

MST=1,TRX=1,BB=0,PIN=1,I2CM=1

§ I2CxCR2_SWRES_01

#define I2CxCR2_SWRES_01   ((uint32_t)0x00000001)

SWRES=01

§ I2CxCR2_SWRES_10

#define I2CxCR2_SWRES_10   ((uint32_t)0x00000002)

SWRES=10

§ I2CxDBR_DB_MASK

#define I2CxDBR_DB_MASK   ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */

§ I2CxIE_CLEAR

#define I2CxIE_CLEAR   ((uint32_t)0x00000000)

All Clear Setting

§ I2CxIE_DMARI2CRX

#define I2CxIE_DMARI2CRX   ((uint32_t)0x00000010)

DMARI2CRX

§ I2CxIE_DMARI2CTX

#define I2CxIE_DMARI2CTX   ((uint32_t)0x00000020)

DMARI2CTX

§ I2CxIE_I2C

#define I2CxIE_I2C   ((uint32_t)0x00000001)

INTI2C

§ I2CxIE_SELPINCD

#define I2CxIE_SELPINCD   ((uint32_t)0x00000040)

SELPINCD

§ I2CxOP_DISAL

#define I2CxOP_DISAL   ((uint32_t)0x00000080)

DISAL

§ I2CxOP_GCDI

#define I2CxOP_GCDI   ((uint32_t)0x00000004)

GDDI

§ I2CxOP_INIT

#define I2CxOP_INIT   ((uint32_t)0x00000084)

Initial Settings.

§ I2CxOP_MFACK

#define I2CxOP_MFACK   ((uint32_t)0x00000001)

MFACK

§ I2CxOP_NFSEL

#define I2CxOP_NFSEL   ((uint32_t)0x00000010)

NFSEL

§ I2CxOP_RSTA

#define I2CxOP_RSTA   ((uint32_t)0x00000008)

RSTA

§ I2CxOP_SA2ST

#define I2CxOP_SA2ST   ((uint32_t)0x00000040)

SA2ST

§ I2CxOP_SAST

#define I2CxOP_SAST   ((uint32_t)0x00000020)

SAST

§ I2CxOP_SLAVE_INIT

#define I2CxOP_SLAVE_INIT   ((uint32_t)0x00000084)

Slave Initial Settings.

§ I2CxOP_SREN

#define I2CxOP_SREN   ((uint32_t)0x00000002)

SREN

§ I2CxPM_SDA_SCL

#define I2CxPM_SDA_SCL   ((uint32_t)0x00000003) /* SDA and SCL level. */

§ I2CxPRS_PRCK

#define I2CxPRS_PRCK   ((uint32_t)0x0000001F)

PRCK

§ I2CxSR_AAS

#define I2CxSR_AAS   ((uint32_t)0x00000004)

AAS

§ I2CxSR_AD0

#define I2CxSR_AD0   ((uint32_t)0x00000002)

AD0

§ I2CxSR_AL

#define I2CxSR_AL   ((uint32_t)0x00000008)

AL

§ I2CxSR_BB

#define I2CxSR_BB   ((uint32_t)0x00000020)

BB

§ I2CxSR_LRB

#define I2CxSR_LRB   ((uint32_t)0x00000001)

LRB

§ I2CxSR_MST

#define I2CxSR_MST   ((uint32_t)0x00000080)

MST

§ I2CxSR_PIN

#define I2CxSR_PIN   ((uint32_t)0x00000010)

PIN

§ I2CxSR_TRX

#define I2CxSR_TRX   ((uint32_t)0x00000040)

TRX

§ I2CxST_CLEAR

#define I2CxST_CLEAR   ((uint32_t)0x0000000F)

All Bits Clear.

§ I2CxST_I2C

#define I2CxST_I2C   ((uint32_t)0x00000001)

I2C Interrupt Status.

§ I2CxST_I2CAL

#define I2CxST_I2CAL   ((uint32_t)0x00000002)

I2CAL Interrupt Status.

§ I2CxST_I2CBF

#define I2CxST_I2CBF   ((uint32_t)0x00000004)

I2CBF Interrupt Status.

§ I2CxST_NACK

#define I2CxST_NACK   ((uint32_t)0x00000008)

NACK Interrupt Status.

§ I2CxWUPCR_ACK

#define I2CxWUPCR_ACK   ((uint32_t)0x00000020) /* ACK Output. Output "0" */

§ I2CxWUPCR_INT_HOLD

#define I2CxWUPCR_INT_HOLD   ((uint32_t)0x00000000) /* Interrupt setting keep it. */

§ I2CxWUPCR_INT_RELESE

#define I2CxWUPCR_INT_RELESE   ((uint32_t)0x00000001) /* Interrupt Release. */

§ I2CxWUPCR_NACK

#define I2CxWUPCR_NACK   ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */

§ I2CxWUPCR_RST_RELEASE

#define I2CxWUPCR_RST_RELEASE   ((uint32_t)0x00000000) /* I2C BUS Reset Release. */

§ I2CxWUPCR_RST_RESET

#define I2CxWUPCR_RST_RESET   ((uint32_t)0x00000010) /* I2C BUS Reset. */