TMPM4G9
V1.0.0.0
|
Functions | |
TXZ_Result | REG_DAC_DAxREG_set (TSB_DA_TypeDef *p_reg, uint32_t val) |
Set Value DAxREG. More... | |
TXZ_Result | REG_DAC_enable (TSB_DA_TypeDef *p_reg) |
Set DAC Control Enable. More... | |
TXZ_Result | REG_DAC_disable (TSB_DA_TypeDef *p_reg) |
Set DAC Control Disable. More... | |
void | REG_DNFCKCR_set (TSB_DNF_TypeDef *p_reg, uint32_t clock) |
Set Value Noise Filter Clock Select. More... | |
uint32_t | REG_DNFCKCR_get (TSB_DNF_TypeDef *p_reg) |
Get value Noise Filter Clock Select. More... | |
void | REG_DNFENCR_enable (TSB_DNF_TypeDef *p_reg, uint32_t bit) |
Set Interrupt Noise Filter Control. More... | |
void | REG_DNFENCR_disable (TSB_DNF_TypeDef *p_reg, uint32_t bit) |
Set Interrupt Noise Filter Control. More... | |
uint32_t | REG_DNFENCR_get (TSB_DNF_TypeDef *p_reg) |
Get the Interrupt Noise Filter Control. More... | |
void | REG_OFDWEN_disable (TSB_OFD_TypeDef *p_reg) |
Register Write Disable. More... | |
void | REG_OFDWEN_enable (TSB_OFD_TypeDef *p_reg) |
Register Write Enable. More... | |
void | REG_OFDEN_disable (TSB_OFD_TypeDef *p_reg) |
OFD Detection Disable. More... | |
void | REG_OFDEN_enable (TSB_OFD_TypeDef *p_reg) |
OFD Detection Enablel. More... | |
void | REG_OFDMN0_set (TSB_OFD_TypeDef *p_reg, uint32_t param) |
Set Value Detect Minimum Frequency for EHOSC. More... | |
void | REG_OFDMN1_set (TSB_OFD_TypeDef *p_reg, uint32_t param) |
Set Value Detect Minimum Frequency for fc. More... | |
void | REG_OFDMX0_set (TSB_OFD_TypeDef *p_reg, uint32_t param) |
Set Value Detect Maxmun Frequency for EHOSC. More... | |
void | REG_OFDMX1_set (TSB_OFD_TypeDef *p_reg, uint32_t param) |
Set Value Detect Maxmun Frequency for fc. More... | |
void | REG_OFDRST_disable (TSB_OFD_TypeDef *p_reg) |
OFD RESET Disable. More... | |
void | REG_OFDRST_enable (TSB_OFD_TypeDef *p_reg) |
OFD RESET Enable. More... | |
void | REG_OFDSTAT_get (TSB_OFD_TypeDef *p_reg, uint32_t *status) |
Get Value OFD Status Register. More... | |
void | REG_OFDMON1_set (TSB_OFD_TypeDef *p_reg, uint32_t param) |
Set Value Detect Clock. More... | |
TXZ_Result REG_DAC_DAxREG_set | ( | TSB_DA_TypeDef * | p_reg, |
uint32_t | val | ||
) |
Set Value DAxREG.
p_reg | :Register Base Address. |
val | :Setting Value |
- |
Register | Bit Symbol |
---|---|
DAxREG | DAC[7:0] |
TXZ_Result REG_DAC_disable | ( | TSB_DA_TypeDef * | p_reg | ) |
Set DAC Control Disable.
p_reg | :Register Base Address. |
- |
Register | Bit Symbol |
---|---|
DAxCR | [Bit0]: DAC |
TXZ_Result REG_DAC_enable | ( | TSB_DA_TypeDef * | p_reg | ) |
Set DAC Control Enable.
p_reg | :Register Base Address. |
- |
Register | Bit Symbol |
---|---|
DAxCR | [Bit0]: DAC |
uint32_t REG_DNFCKCR_get | ( | TSB_DNF_TypeDef * | p_reg | ) |
Get value Noise Filter Clock Select.
p_reg | :Register Base Address. |
value | :DNFCKCR_NFCKS. |
Register | Bit Symbol |
---|---|
DNFCKCR | NFCKS |
void REG_DNFCKCR_set | ( | TSB_DNF_TypeDef * | p_reg, |
uint32_t | clock | ||
) |
Set Value Noise Filter Clock Select.
p_reg | :Register Base Address. |
clock | :DNFCKCR_NFCKS |
- |
Register | Bit Symbol |
---|---|
DNFCKCR | NFCKS |
void REG_DNFENCR_disable | ( | TSB_DNF_TypeDef * | p_reg, |
uint32_t | bit | ||
) |
Set Interrupt Noise Filter Control.
p_reg | :Register Base Address. |
bit | :Interrupt. :This parameter can be one of the following values: :REG_DNF_NFENCR_NFEN0_MASK :REG_DNF_NFENCR_NFEN1_MASK :REG_DNF_NFENCR_NFEN2_MASK :REG_DNF_NFENCR_NFEN3_MASK :REG_DNF_NFENCR_NFEN4_MASK :REG_DNF_NFENCR_NFEN5_MASK :REG_DNF_NFENCR_NFEN6_MASK :REG_DNF_NFENCR_NFEN7_MASK :REG_DNF_NFENCR_NFEN8_MASK :REG_DNF_NFENCR_NFEN9_MASK :REG_DNF_NFENCR_NFEN10_MASK |
- |
Register | Bit Symbol |
---|---|
NFENCR | NFEN0 |
NFEN1 | |
NFEN2 | |
NFEN3 | |
NFEN4 | |
NFEN5 | |
NFEN6 | |
NFEN7 | |
NFEN8 | |
NFEN9 | |
NFEN10 |
void REG_DNFENCR_enable | ( | TSB_DNF_TypeDef * | p_reg, |
uint32_t | bit | ||
) |
Set Interrupt Noise Filter Control.
p_reg | :Register Base Address. |
bit | :Interrupt. :This parameter can be one of the following values: :REG_DNF_NFENCR_NFEN0_MASK :REG_DNF_NFENCR_NFEN1_MASK :REG_DNF_NFENCR_NFEN2_MASK :REG_DNF_NFENCR_NFEN3_MASK :REG_DNF_NFENCR_NFEN4_MASK :REG_DNF_NFENCR_NFEN5_MASK :REG_DNF_NFENCR_NFEN6_MASK :REG_DNF_NFENCR_NFEN7_MASK :REG_DNF_NFENCR_NFEN8_MASK :REG_DNF_NFENCR_NFEN9_MASK :REG_DNF_NFENCR_NFEN10_MASK |
- |
Register | Bit Symbol |
---|---|
NFENCR | NFEN0 |
NFEN1 | |
NFEN2 | |
NFEN3 | |
NFEN4 | |
NFEN5 | |
NFEN6 | |
NFEN7 | |
NFEN8 | |
NFEN9 | |
NFEN10 |
uint32_t REG_DNFENCR_get | ( | TSB_DNF_TypeDef * | p_reg | ) |
Get the Interrupt Noise Filter Control.
p_reg | :Register Base Address. |
value | :NFENCR. |
Register | Bit Symbol |
---|---|
NFENCR | NFEN0 |
NFEN1 | |
NFEN2 | |
NFEN3 | |
NFEN4 | |
NFEN5 | |
NFEN6 | |
NFEN7 | |
NFEN8 | |
NFEN9 | |
NFEN10 |
void REG_OFDEN_disable | ( | TSB_OFD_TypeDef * | p_reg | ) |
OFD Detection Disable.
p_reg | :Register Base Address. |
- |
- |
Register | Bit Symbol |
---|---|
OFDCR2 | :— |
OFDEN |
void REG_OFDEN_enable | ( | TSB_OFD_TypeDef * | p_reg | ) |
OFD Detection Enablel.
p_reg | :Register Base Address. |
- |
- |
Register | Bit Symbol |
---|---|
OFDCR2 | :— |
OFDEN |
void REG_OFDMN0_set | ( | TSB_OFD_TypeDef * | p_reg, |
uint32_t | param | ||
) |
Set Value Detect Minimum Frequency for EHOSC.
p_reg | :Register Base Address. |
param | :Set Value |
- |
Register | Bit Symbol |
---|---|
OFDMN0 | :— |
OFDMN0 |
void REG_OFDMN1_set | ( | TSB_OFD_TypeDef * | p_reg, |
uint32_t | param | ||
) |
Set Value Detect Minimum Frequency for fc.
p_reg | :Register Base Address. |
param | :Set Value |
- |
Register | Bit Symbol |
---|---|
OFDM1 | :— |
OFDMN1 |
void REG_OFDMON1_set | ( | TSB_OFD_TypeDef * | p_reg, |
uint32_t | param | ||
) |
Set Value Detect Clock.
p_reg | :Register Base Address. |
param | :OFDMON1. |
- |
Register | Bit Symbol |
---|---|
OFDMON1 | :— |
OFDMON1 |
void REG_OFDMX0_set | ( | TSB_OFD_TypeDef * | p_reg, |
uint32_t | param | ||
) |
Set Value Detect Maxmun Frequency for EHOSC.
p_reg | :Register Base Address. |
param | :Set Value |
- |
Register | Bit Symbol |
---|---|
OFDMN0 | :— |
OFDMN0 |
void REG_OFDMX1_set | ( | TSB_OFD_TypeDef * | p_reg, |
uint32_t | param | ||
) |
Set Value Detect Maxmun Frequency for fc.
p_reg | :Register Base Address. |
param | :Set Value |
- |
Register | Bit Symbol |
---|---|
OFDM1 | :— |
OFDMN1 |
void REG_OFDRST_disable | ( | TSB_OFD_TypeDef * | p_reg | ) |
OFD RESET Disable.
p_reg | :Register Base Address. |
- |
- |
Register | Bit Symbol |
---|---|
OFDRST | :— |
OFDRSTEN |
void REG_OFDRST_enable | ( | TSB_OFD_TypeDef * | p_reg | ) |
OFD RESET Enable.
p_reg | :Register Base Address. |
- |
- |
Register | Bit Symbol |
---|---|
OFDRST | :— |
OFDRSTEN |
void REG_OFDSTAT_get | ( | TSB_OFD_TypeDef * | p_reg, |
uint32_t * | status | ||
) |
Get Value OFD Status Register.
p_reg | :Register Base Address. |
status | : status value store address |
- |
Register | Bit Symbol |
---|---|
OFDSTAT | :— |
OFDBUSY | |
FRQERR |
void REG_OFDWEN_disable | ( | TSB_OFD_TypeDef * | p_reg | ) |
Register Write Disable.
p_reg | :Register Base Address. |
- |
- |
Register | Bit Symbol |
---|---|
OFDCR1 | :— |
OFDWEN |
void REG_OFDWEN_enable | ( | TSB_OFD_TypeDef * | p_reg | ) |
Register Write Enable.
p_reg | :Register Base Address. |
- |
- |
Register | Bit Symbol |
---|---|
OFDCR1 | :— |
OFDWEN |