TMPM4G9
V1.0.0.0
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[Bit2-0]: Noise Filter Clock Select. More...
Macros | |
#define | REG_DNF_NFCKCR_NFCKS_STOP ((uint32_t)0x00000000) |
#define | REG_DNF_NFCKCR_NFCKS_CLOCK_2 ((uint32_t)0x00000001) |
#define | REG_DNF_NFCKCR_NFCKS_CLOCK_4 ((uint32_t)0x00000002) |
#define | REG_DNF_NFCKCR_NFCKS_CLOCK_8 ((uint32_t)0x00000003) |
#define | REG_DNF_NFCKCR_NFCKS_CLOCK_16 ((uint32_t)0x00000004) |
#define | REG_DNF_NFCKCR_NFCKS_CLOCK_32 ((uint32_t)0x00000005) |
#define | REG_DNF_NFCKCR_NFCKS_CLOCK_64 ((uint32_t)0x00000006) |
#define | REG_DNF_NFCKCR_NFCKS_CLOCK_128 ((uint32_t)0x00000007) |
[Bit2-0]: Noise Filter Clock Select.
#define REG_DNF_NFCKCR_NFCKS_CLOCK_128 ((uint32_t)0x00000007) |
fc/128 fc=20MHz:44.8us 40MHz:22.4us 80MHz:11.2us 100MHz:8.96us
#define REG_DNF_NFCKCR_NFCKS_CLOCK_16 ((uint32_t)0x00000004) |
fc/16 fc=20MHz: 5.6us 40MHz: 2.8us 80MHz: 1.4us 100MHz:1.12us
#define REG_DNF_NFCKCR_NFCKS_CLOCK_2 ((uint32_t)0x00000001) |
fc/2 fc=20MHz: 0.7us 40MHz: 0.35us 80MHz: 0.175us 100MHz:0.14us
#define REG_DNF_NFCKCR_NFCKS_CLOCK_32 ((uint32_t)0x00000005) |
fc/32 fc=20MHz:11.2us 40MHz: 5.6us 80MHz: 2.8us 100MHz:2.24us
#define REG_DNF_NFCKCR_NFCKS_CLOCK_4 ((uint32_t)0x00000002) |
fc/4 fc=20MHz: 1.4us 40MHz: 0.7us 80MHz: 0.35us 100MHz:0.28us
#define REG_DNF_NFCKCR_NFCKS_CLOCK_64 ((uint32_t)0x00000006) |
fc/64 fc=20MHz:22.4us 40MHz:11.2us 80MHz: 5.6us 100MHz:4.48us
#define REG_DNF_NFCKCR_NFCKS_CLOCK_8 ((uint32_t)0x00000003) |
fc/8 fc=20MHz: 2.8us 40MHz: 1.4us 80MHz: 0.7us 100MHz:0.56us
#define REG_DNF_NFCKCR_NFCKS_STOP ((uint32_t)0x00000000) |
Clock Control circuit stop.