TMPM4G(1) Group Peripheral Driver User Manual  V1.0.0.0
txz_tspi.h
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1 
13 /*------------------------------------------------------------------------------*/
14 /* Define to prevent recursive inclusion */
15 /*------------------------------------------------------------------------------*/
16 #ifndef __TSPI_H
17 #define __TSPI_H
18 
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22 
23 /*------------------------------------------------------------------------------*/
24 /* Includes */
25 /*------------------------------------------------------------------------------*/
26 #include "txz_driver_def.h"
39 /*------------------------------------------------------------------------------*/
40 /* Macro Definition */
41 /*------------------------------------------------------------------------------*/
51 #define TSPI_NULL ((void *)0)
52  /* End of group TSPI_NullPointer */
55 
61 #define TSPI_PARAM_OK ((int32_t)1)
62 #define TSPI_PARAM_NG ((int32_t)0) /* End of group TSPI_ParameterResult */
66 
67 
73 #define TSPI_RESULT_SUCCESS (0)
74 #define TSPI_RESULT_FAILURE (-1) /* End of group TSPI_Result */
78 
84 #define TSPI_RESET10 ((uint32_t)0x00000080)
85 #define TSPI_RESET01 ((uint32_t)0x00000040) /* End of group TSPI_SW_Reset */
89 
90 
96 #define TSPI_DISABLE ((uint32_t)0x00000000)
97 #define TSPI_ENABLE ((uint32_t)0x00000001) /* End of group TSPI_Enable */
101 
107 #define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000)
108 #define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /* End of group TSPI_Transmission_Control */
112 
118 #define TSPI_TRXE_DISABLE ((uint32_t)0x00000000)
119 #define TSPI_TRXE_ENABLE ((uint32_t)0x00004000)
120 #define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /* End of group TSPI_Transmission_Control */
124 
130 #define TSPI_SPI_MODE ((uint32_t)0x00000000)
131 #define TSPI_SIO_MODE ((uint32_t)0x00002000) /* End of group TSPI_Transmission_Mode */
135 
136 
142 #define TSPI_MASTER_OPERATION ((uint32_t)0x00001000)
143 #define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /* End of group TSPI_Operation_Select */
147 
148 
154 #define TSPI_TX_ONLY ((uint32_t)0x00000400)
155 #define TSPI_RX_ONLY ((uint32_t)0x00000800)
156 #define TSPI_TWO_WAY ((uint32_t)0x00000C00)
157 #define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /* End of group TSPI_Transfer_Mode */
161 
162 
168 #define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000)
169 #define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100)
170 #define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200)
171 #define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /* End of group TSPI_CSSEL_Select */
175 
181 #define TSPI_TRANS_RANGE_CONTINUE ((uint32_t)0x00000000)
182 #define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000001)
183 #define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /* End of group TSPI_Transfer_Frame_Range */
187 
192 #define TSPI_TIDLE_Hiz ((uint32_t)0x00000000)
193 #define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000)
194 #define TSPI_TIDLE_LOW ((uint32_t)0x00800000)
195 #define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /* End of group TSPI_IDLE_Output_value */
199 
205 #define TSPI_RXDLY_SET ((uint32_t)0x00010000) /* End of group TSPI_RXDLY_value*/
209 
210 
216 #define TSPI_TXDEMP_LOW ((uint32_t)0x00000000)
217 #define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /* End of group TSPI_Underrun_Output_value */
221 
222 
228 #define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000)
229 #define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000)
230 #define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000)
231 #define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000)
232 #define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000)
233 #define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000)
234 #define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000)
235 #define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000)
236 #define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /* End of group TSPI_TxFillLevel */
240 
241 
247 #define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100)
248 #define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200)
249 #define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300)
250 #define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400)
251 #define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500)
252 #define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600)
253 #define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700)
254 #define TSPI_RX_FILL_LEVEL_8 ((uint32_t)0x00000800)
255 #define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000F00) /* End of group TSPI_RxFillLevel */
259 
260 
266 #define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000)
267 #define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /* End of group TSPI_TxFIFOInterrupt */
271 
272 
278 #define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000)
279 #define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /* End of group TSPI_TxInterrupt */
283 
284 
290 #define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000)
291 #define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /* End of group TSPI_RxFIFOInterrupt */
295 
296 
302 #define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000)
303 #define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /* End of group TSPI_RxInterrupt */
307 
308 
314 #define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000)
315 #define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /* End of group TSPI_ErrorInterrupt */
319 
320 
326 #define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002)
327 #define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000)
328 #define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /* End of group TSPI_TxDMAInterrupt */
332 
333 
339 #define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001)
340 #define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000)
341 #define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /* End of group TSPI_RxDMAInterrupt */
345 
346 
352 #define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000)
353 #define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /* End of group TSPI_Tx_Buffer_Clear */
357 
358 
364 #define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000)
365 #define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /* End of group TSPI_Rx_Buffer_Clear */
369 
370 
376 #define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000)
377 #define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010)
378 #define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020)
379 #define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030)
380 #define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040)
381 #define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050)
382 #define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060)
383 #define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070)
384 #define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080)
385 #define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /* End of group TSPI_Baudrate_Clock */
389 
390 
396 #define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000)
397 #define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001)
398 #define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002)
399 #define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003)
400 #define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004)
401 #define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005)
402 #define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006)
403 #define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007)
404 #define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008)
405 #define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009)
406 #define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a)
407 #define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b)
408 #define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c)
409 #define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d)
410 #define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e)
411 #define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /* End of group TSPI_Baudrate_Divider */
415 
416 
422 #define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000)
423 #define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /* End of group TSPI_DataDirection */
427 
428 
434 #define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000)
435 #define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000)
436 #define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000)
437 #define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000)
438 #define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000)
439 #define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000)
440 #define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000)
441 #define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000)
442 #define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000)
443 #define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000)
444 #define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000)
445 #define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000)
446 #define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000)
447 #define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000)
448 #define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000)
449 #define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000)
450 #define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000)
451 #define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000)
452 #define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000)
453 #define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000)
454 #define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000)
455 #define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000)
456 #define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000)
457 #define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000)
458 #define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000)
459 #define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /* End of group TSPI_DataLength */
463 
464 
470 #define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000)
471 #define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000)
472 #define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000)
473 #define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000)
474 #define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000)
475 #define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000)
476 #define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000)
477 #define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000)
478 #define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000)
479 #define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000)
480 #define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000)
481 #define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000)
482 #define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000)
483 #define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000)
484 #define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000)
485 #define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /* End of group TSPI_Frame_Interval_Time */
489 
490 
496 #define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000)
497 #define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /* End of group TSPI_TSPIxCS3_Polarity */
501 
502 
508 #define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000)
509 #define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /* End of group TSPI_TSPIxCS2_Polarity */
513 
514 
520 #define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000)
521 #define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /* End of group TSPI_TSPIxCS1_Polarity */
525 
526 
532 #define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000)
533 #define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /* End of group TSPI_TSPIxCS0_Polarity */
537 
538 
544 #define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000)
545 #define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /* End of group Serial Clock Polarity */
549 
550 
556 #define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000)
557 #define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /* End of group TSPI_Serial_Clock_IDLE_Polarity */
561 
562 
568 #define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400)
569 #define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800)
570 #define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00)
571 #define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000)
572 #define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400)
573 #define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800)
574 #define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00)
575 #define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000)
576 #define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400)
577 #define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800)
578 #define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00)
579 #define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000)
580 #define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400)
581 #define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800)
582 #define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /* End of group TSPI_Minimum_IDLE_Time */
586 
587 
593 #define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000)
594 #define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010)
595 #define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020)
596 #define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030)
597 #define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040)
598 #define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050)
599 #define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060)
600 #define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070)
601 #define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080)
602 #define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090)
603 #define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0)
604 #define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0)
605 #define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0)
606 #define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0)
607 #define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0)
608 #define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /* End of group TSPI_Serial_Clock_Delay */
612 
613 
619 #define TSPI_NEGATE_1 ((uint32_t)0x00000000)
620 #define TSPI_NEGATE_2 ((uint32_t)0x00000001)
621 #define TSPI_NEGATE_3 ((uint32_t)0x00000002)
622 #define TSPI_NEGATE_4 ((uint32_t)0x00000003)
623 #define TSPI_NEGATE_5 ((uint32_t)0x00000004)
624 #define TSPI_NEGATE_6 ((uint32_t)0x00000005)
625 #define TSPI_NEGATE_7 ((uint32_t)0x00000006)
626 #define TSPI_NEGATE_8 ((uint32_t)0x00000007)
627 #define TSPI_NEGATE_9 ((uint32_t)0x00000008)
628 #define TSPI_NEGATE_10 ((uint32_t)0x00000009)
629 #define TSPI_NEGATE_11 ((uint32_t)0x0000000a)
630 #define TSPI_NEGATE_12 ((uint32_t)0x0000000b)
631 #define TSPI_NEGATE_13 ((uint32_t)0x0000000c)
632 #define TSPI_NEGATE_14 ((uint32_t)0x0000000d)
633 #define TSPI_NEGATE_15 ((uint32_t)0x0000000e)
634 #define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /* End of group TSPI_Negate_Delay */
638 
639 
645 #define TSPI_PARITY_DISABLE ((uint32_t)0x00000000)
646 #define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /* End of group TSPI_ParityEnable */
650 
651 
657 #define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000)
658 #define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /* End of group TSPI_ParityBit */
662 
663 
669 #define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000)
670 #define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /* End of group TSPI_Status_Setting_flag */
674 
675 
681 #define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000)
682 #define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000)
683 #define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /* End of group TSPI_TxState */
687 
688 
694 #define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000)
695 #define TSPI_TX_DONE ((uint32_t)0x00400000)
696 #define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /* End of group TSPI_TxDone */
700 
701 
707 #define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000)
708 #define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000)
709 #define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /* End of group TSPI_TxFIFOInterruptFlag */
713 
719 #define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000)
720 #define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /* End of group TSPI_TxFIFOEmptyFlag */
724 
730 #define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000)
731 #define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000)
732 #define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000)
733 #define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000)
734 #define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000)
735 #define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000)
736 #define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000)
737 #define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000)
738 #define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /* End of group TSPI_TxReachFillLevel */
742 
743 
749 #define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000)
750 #define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080)
751 #define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /* End of group TSPI_RxState */
755 
756 
762 #define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040)
763 #define TSPI_RX_DONE ((uint32_t)0x00000040)
764 #define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /* End of group TSPI_RxDone */
768 
769 
775 #define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000)
776 #define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020)
777 #define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /* End of group TSPI_RxFIFOInterruptFlag */
781 
787 #define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000)
788 #define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /* End of group TSPI_RxFIFOFullFlag */
792 
793 
799 #define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000)
800 #define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001)
801 #define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002)
802 #define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003)
803 #define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004)
804 #define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005)
805 #define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006)
806 #define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007)
807 #define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /* End of group TSPI_RxReachFillLevel */
811 
812 
818 #define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000)
819 #define TSPI_TRGERR_ERR ((uint32_t)0x00000008)
820 #define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /* End of group TSPI_TRGErr */
824 
830 #define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000)
831 #define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004)
832 #define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /* End of group TSPI_UnderrunErr */
836 
842 #define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000)
843 #define TSPI_OVERRUN_ERR ((uint32_t)0x00000002)
844 #define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /* End of group TSPI_OverrunErr */
848 
849 
855 #define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000)
856 #define TSPI_PARITY_ERR ((uint32_t)0x00000001)
857 #define TSPI_PARITY_MASK ((uint32_t)0x00000001) /* End of group TSPI_ParityErr */
861 
867 #define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000)
868 #define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001)
869 #define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /* End of group TSPI_Data_allign */
873 
879 #define TSPI_FIFO_MAX ((uint32_t)0x00000008) /* End of group TSPI_FifoMax */
883 
889 #define NOERROR ((uint32_t)0x00000000)
890 #define TIMEOUTERR ((uint32_t)0x00000001)
891 #define DATALENGTHERR ((uint32_t)0x00000002)
892 #define DATABUFEMPERR ((uint32_t)0x00000003)
893 #define DATALACKERR ((uint32_t)0x00000004)
894 #define FIFOFULLERR ((uint32_t)0x00000005)
895 #define TRANSMITMODEERR ((uint32_t)0x00000006)
896 #define UNDERRUNERR ((uint32_t)0x00000007)
897 #define OVERRUNERR ((uint32_t)0x00000008)
898 #define PARITYERR ((uint32_t)0x00000009)
899 #define INITERR ((uint32_t)0x000000) /* End of group TSPI_ErrCode */
903 
909 #define BUFFSIZE ((uint32_t)0x000000010 /* End of group TSPI_Buffer_Size */
913  /* End of group TSPI_Exported_define */
916 
917 /*------------------------------------------------------------------------------*/
918 /* Enumerated Type Definition */
919 /*------------------------------------------------------------------------------*/
924 /* No define */ /* End of group TSPI_Exported_Typedef */
928 /*------------------------------------------------------------------------------*/
929 /* Structure Definition */
930 /*------------------------------------------------------------------------------*/
935 /*----------------------------------*/
941 /*----------------------------------*/
942 typedef struct
943 {
944  uint8_t *p_data;
945  uint32_t num;
947 
948 /*----------------------------------*/
954 /*----------------------------------*/
955 typedef struct
956 {
957  uint16_t *p_data;
958  uint32_t num;
960 
966 /*----------------------------------*/
967 typedef struct
968 {
969  uint32_t *p_data;
970  uint32_t num;
972 
973 /*----------------------------------*/
978 /*----------------------------------*/
979 typedef union
980 {
985 
986 /*----------------------------------*/
992 /*----------------------------------*/
993 typedef struct
994 {
995  uint8_t *p_data;
996  uint32_t num;
998 
999 /*----------------------------------*/
1005 /*----------------------------------*/
1006 typedef struct
1007 {
1008  uint16_t *p_data;
1009  uint32_t num;
1011 /*----------------------------------*/
1017 /*----------------------------------*/
1018 typedef struct
1019 {
1020  uint32_t *p_data;
1021  uint32_t num;
1023 
1024 /*----------------------------------*/
1029 /*----------------------------------*/
1030 typedef union
1031 {
1035 } tspi_transmit_t;
1036 
1037 /*----------------------------------*/
1042 /*----------------------------------*/
1043 typedef struct
1044 {
1045  uint32_t trgen;
1047  uint32_t trxe;
1049  uint32_t tspims;
1051  uint32_t mstr;
1053  uint32_t tmmd;
1055  uint32_t cssel;
1057  uint32_t fc;
1059 } tspi_control1_t;
1060 
1061 /*----------------------------------*/
1066 /*----------------------------------*/
1067 typedef struct
1068 {
1069  uint32_t tidle;
1071  uint32_t txdemp;
1073  uint32_t rxdly;
1075  uint32_t til;
1077  uint32_t ril;
1079  uint32_t inttxfe;
1081  uint32_t inttxwe;
1083  uint32_t intrxfe;
1085  uint32_t intrxwe;
1087  uint32_t interr;
1089  uint32_t dmate;
1091  uint32_t dmare;
1093 } tspi_control2_t;
1094 
1095 /*----------------------------------*/
1100 /*----------------------------------*/
1101 typedef struct
1102 {
1103  uint32_t tfempclr;
1105  uint32_t rffllclr;
1107 } tspi_control3_t;
1108 
1109 /*----------------------------------*/
1114 /*----------------------------------*/
1115 typedef struct
1116 {
1117  uint32_t brck;
1119  uint32_t brs;
1121 } tspi_baudrate_t;
1122 
1123 /*----------------------------------*/
1128 /*----------------------------------*/
1129 typedef struct
1130 {
1131  uint32_t dir;
1133  uint32_t fl;
1135  uint32_t fint;
1137  uint32_t cs3pol;
1139  uint32_t cs2pol;
1141  uint32_t cs1pol;
1143  uint32_t cs0pol;
1145  uint32_t ckpha;
1147  uint32_t ckpol;
1149  uint32_t csint;
1151  uint32_t cssckdl;
1153  uint32_t sckcsdl;
1155 } tspi_fmtr0_t;
1156 
1157 /*----------------------------------*/
1162 /*----------------------------------*/
1163 typedef struct
1164 {
1165  uint32_t reserved;
1167  uint32_t vpe;
1169  uint32_t vpm;
1171 } tspi_fmtr1_t;
1172 
1173 /*----------------------------------*/
1178 /*----------------------------------*/
1179 typedef struct
1180 {
1181  uint32_t tspisue;
1183  uint32_t txrun;
1185  uint32_t txend;
1187  uint32_t inttxwf;
1189  uint32_t tfemp;
1191  uint32_t tlvll;
1193  uint32_t rxrun;
1195  uint32_t rxend;
1197  uint32_t intrxff;
1199  uint32_t rffll;
1201  uint32_t rlvl;
1203 } tspi_status_t;
1204 
1205 /*----------------------------------*/
1210 /*----------------------------------*/
1211 typedef struct
1212 {
1213  uint32_t udrerr;
1215  uint32_t ovrerr;
1217  uint32_t perr;
1219 } tspi_error_t;
1220 
1221 
1222 /*----------------------------------*/
1227 /*----------------------------------*/
1228 typedef struct
1229 {
1230  uint32_t id;
1244 
1245 /*----------------------------------*/
1249 /*----------------------------------*/
1250 typedef struct tspi_handle
1251 {
1252  TSB_TSPI_TypeDef *p_instance;
1254  uint32_t errcode;
1255  /*------------------------------------------*/
1259  /*------------------------------------------*/
1260  struct
1261  {
1262  uint32_t rp;
1264  uint8_t tx_allign;
1265  void (*handler)(uint32_t id, TXZ_Result result);
1266  } transmit;
1267  /*------------------------------------------*/
1271  /*------------------------------------------*/
1272  struct
1273  {
1275  uint8_t rx_allign;
1276  void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info);
1277  } receive;
1278 } tspi_t; /* End of group TSPI_Exported_Typedef */
1282 
1283 
1284 /*------------------------------------------------------------------------------*/
1285 /* Functions */
1286 /*------------------------------------------------------------------------------*/
1291 TXZ_Result tspi_init(tspi_t *p_obj);
1292 TXZ_Result tspi_deinit(tspi_t *p_obj);
1293 TXZ_Result tspi_format(tspi_t *p_obj);
1294 TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout);
1295 TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout);
1300 void tspi_irq_handler_transmit(tspi_t *p_obj);
1301 void tspi_irq_handler_receive(tspi_t *p_obj);
1302 void tspi_error_irq_handler(tspi_t *p_obj);
1303 TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status);
1304 TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error);
1307 TXZ_Result tspi_discard_receive(tspi_t *p_obj); /* End of group TSPI_Exported_functions */ /* End of group TSPI */ /* End of group Periph_Driver */
1317 
1318 #ifdef __cplusplus
1319 }
1320 #endif /* __cplusplus */
1321 #endif /* __TSPI_H */
1322 
1323 
uint32_t txdemp
Definition: txz_tspi.h:1071
uint32_t rffll
Definition: txz_tspi.h:1199
uint32_t fint
Definition: txz_tspi.h:1135
uint32_t tspisue
Definition: txz_tspi.h:1181
uint32_t trxe
Definition: txz_tspi.h:1047
TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout)
uint32_t inttxfe
Definition: txz_tspi.h:1079
uint32_t reserved
Definition: txz_tspi.h:1165
uint32_t rffllclr
Definition: txz_tspi.h:1105
tspi_control2_t cnt2
Definition: txz_tspi.h:1233
uint32_t til
Definition: txz_tspi.h:1075
Format control1.
Definition: txz_tspi.h:1163
uint32_t cs0pol
Definition: txz_tspi.h:1143
TSPI handle structure definition.
Definition: txz_tspi.h:1250
uint32_t trgen
Definition: txz_tspi.h:1045
Format control0.
Definition: txz_tspi.h:1129
Receive event information structure definition.
Definition: txz_tspi.h:967
uint32_t ovrerr
Definition: txz_tspi.h:1215
tspi_baudrate_t brd
Definition: txz_tspi.h:1237
uint32_t tidle
Definition: txz_tspi.h:1069
uint32_t brs
Definition: txz_tspi.h:1119
tspi_transmit16_t tx16
Definition: txz_tspi.h:1033
Transmit data information structure definition.
Definition: txz_tspi.h:1018
TSB_TSPI_TypeDef * p_instance
Definition: txz_tspi.h:1252
TXZ_Result
Definition: txz_driver_def.h:43
tspi_initial_setting_t init
Definition: txz_tspi.h:1253
uint32_t errcode
Definition: txz_tspi.h:1254
uint32_t inttxwe
Definition: txz_tspi.h:1081
tspi_transmit8_t tx8
Definition: txz_tspi.h:1032
struct tspi_handle tspi_t
TSPI handle structure definition.
Receive event information structure definition.
Definition: txz_tspi.h:955
Receive event information structure definition.
Definition: txz_tspi.h:979
uint8_t * p_data
Definition: txz_tspi.h:995
tspi_control1_t cnt1
Definition: txz_tspi.h:1231
uint32_t csint
Definition: txz_tspi.h:1149
uint16_t * p_data
Definition: txz_tspi.h:957
TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error)
Clock setting structure definition.
Definition: txz_tspi.h:1115
uint32_t tlvll
Definition: txz_tspi.h:1191
TXZ_Result tspi_error_clear(tspi_t *p_obj)
uint32_t cs1pol
Definition: txz_tspi.h:1141
tspi_fmtr1_t fmr1
Definition: txz_tspi.h:1241
Receive event information structure definition.
Definition: txz_tspi.h:942
void tspi_irq_handler_receive(tspi_t *p_obj)
uint32_t rp
Definition: txz_tspi.h:1262
uint32_t num
Definition: txz_tspi.h:958
Control Setting structure definition.
Definition: txz_tspi.h:1101
uint32_t udrerr
Definition: txz_tspi.h:1213
uint32_t inttxwf
Definition: txz_tspi.h:1187
uint32_t tfemp
Definition: txz_tspi.h:1189
uint32_t fl
Definition: txz_tspi.h:1133
uint32_t intrxff
Definition: txz_tspi.h:1197
Transmit data information structure definition.
Definition: txz_tspi.h:1030
uint32_t txrun
Definition: txz_tspi.h:1183
uint32_t dmate
Definition: txz_tspi.h:1089
Control Setting structure definition.
Definition: txz_tspi.h:1067
uint32_t ckpol
Definition: txz_tspi.h:1147
uint32_t num
Definition: txz_tspi.h:1009
uint32_t num
Definition: txz_tspi.h:996
TXZ_Result tspi_discard_transmit(tspi_t *p_obj)
void tspi_irq_handler_transmit(tspi_t *p_obj)
uint32_t intrxfe
Definition: txz_tspi.h:1083
uint32_t txend
Definition: txz_tspi.h:1185
uint32_t perr
Definition: txz_tspi.h:1217
Initial setting structure definition.
Definition: txz_tspi.h:1228
uint32_t sckcsdl
Definition: txz_tspi.h:1153
uint32_t cs3pol
Definition: txz_tspi.h:1137
void(* handler)(uint32_t id, TXZ_Result result)
Definition: txz_tspi.h:1265
uint32_t rxrun
Definition: txz_tspi.h:1193
uint32_t vpm
Definition: txz_tspi.h:1169
tspi_fmtr0_t fmr0
Definition: txz_tspi.h:1239
uint32_t ril
Definition: txz_tspi.h:1077
struct tspi_handle::@7 transmit
Transmit Information.
Status register.
Definition: txz_tspi.h:1179
All common macro and definition for TXZ peripheral drivers.
uint32_t mstr
Definition: txz_tspi.h:1051
Control Setting structure definition.
Definition: txz_tspi.h:1043
struct tspi_handle::@8 receive
Receive Information.
TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info)
Transmit data information structure definition.
Definition: txz_tspi.h:1006
uint32_t tspims
Definition: txz_tspi.h:1049
TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status)
TXZ_Result tspi_format(tspi_t *p_obj)
tspi_receive_t info
Definition: txz_tspi.h:1274
uint32_t tmmd
Definition: txz_tspi.h:1053
uint32_t num
Definition: txz_tspi.h:1021
uint8_t tx_allign
Definition: txz_tspi.h:1264
TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout)
TXZ_Result tspi_master_dma_transfer(tspi_t *p_obj, tspi_transmit_t *p_info)
TXZ_Result tspi_deinit(tspi_t *p_obj)
uint32_t tfempclr
Definition: txz_tspi.h:1103
void tspi_error_irq_handler(tspi_t *p_obj)
Transmit data information structure definition.
Definition: txz_tspi.h:993
uint32_t brck
Definition: txz_tspi.h:1117
uint32_t cssel
Definition: txz_tspi.h:1055
uint32_t dir
Definition: txz_tspi.h:1131
uint32_t cs2pol
Definition: txz_tspi.h:1139
tspi_transmit32_t tx32
Definition: txz_tspi.h:1034
uint32_t cssckdl
Definition: txz_tspi.h:1151
tspi_receive8_t rx8
Definition: txz_tspi.h:981
uint32_t rlvl
Definition: txz_tspi.h:1201
TXZ_Result tspi_discard_receive(tspi_t *p_obj)
tspi_transmit_t info
Definition: txz_tspi.h:1263
uint32_t * p_data
Definition: txz_tspi.h:1020
uint16_t * p_data
Definition: txz_tspi.h:1008
TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info)
uint32_t intrxwe
Definition: txz_tspi.h:1085
uint32_t rxdly
Definition: txz_tspi.h:1073
uint32_t id
Definition: txz_tspi.h:1230
uint32_t fc
Definition: txz_tspi.h:1057
TXZ_Result tspi_init(tspi_t *p_obj)
uint8_t rx_allign
Definition: txz_tspi.h:1275
tspi_control3_t cnt3
Definition: txz_tspi.h:1235
uint32_t vpe
Definition: txz_tspi.h:1167
uint32_t num
Definition: txz_tspi.h:970
TXZ_Result tspi_master_dma_receive(tspi_t *p_obj, tspi_receive_t *p_info)
uint32_t rxend
Definition: txz_tspi.h:1195
uint32_t interr
Definition: txz_tspi.h:1087
uint32_t num
Definition: txz_tspi.h:945
uint32_t * p_data
Definition: txz_tspi.h:969
uint8_t * p_data
Definition: txz_tspi.h:944
tspi_receive16_t rx16
Definition: txz_tspi.h:982
uint32_t dmare
Definition: txz_tspi.h:1091
uint32_t ckpha
Definition: txz_tspi.h:1145
tspi_receive32_t rx32
Definition: txz_tspi.h:983
Error flag.
Definition: txz_tspi.h:1211