TMPM4G(1) Group Peripheral Driver User Manual  V1.0.0.0
txz_hdma.h
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1 
13 /*------------------------------------------------------------------------------*/
14 /* Define to prevent recursive inclusion */
15 /*------------------------------------------------------------------------------*/
16 #ifndef __HDMA_H
17 #define __HDMA_H
18 
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22 
23 /*------------------------------------------------------------------------------*/
24 /* Includes */
25 /*------------------------------------------------------------------------------*/
26 #include "txz_driver_def.h"
27 
38 /*------------------------------------------------------------------------------*/
39 /* Macro Function */
40 /*------------------------------------------------------------------------------*/
46 /* no define */
47  /* End of group HDMA_Exported_macro */
51 
52 
53 /*------------------------------------------------------------------------------*/
54 /* Macro Definition */
55 /*------------------------------------------------------------------------------*/
66 #define HDMA_CH_NUM ((uint32_t)2) /* End of group HDMA_ChannelNum */
70 
76 #define HDMA_TRANS_TYPE_SINGLE ((uint32_t)0x00000000)
77 #define HDMA_TRANS_TYPE_BURST ((uint32_t)0x00000001) /* End of group HDMA_TransferCompInt */
81 
87 #define HDMA_SRC_REQ_CH_MEM_USE ((uint32_t)0x00000000)
88 #define HDMA_SRC_REQ_CH_1 ((uint32_t)0x00000001)
89 #define HDMA_SRC_REQ_CH_2 ((uint32_t)0x00000002)
90 #define HDMA_SRC_REQ_CH_3 ((uint32_t)0x00000003)
91 #define HDMA_SRC_REQ_CH_4 ((uint32_t)0x00000004)
92 #define HDMA_SRC_REQ_CH_5 ((uint32_t)0x00000005)
93 #define HDMA_SRC_REQ_CH_6 ((uint32_t)0x00000006)
94 #define HDMA_SRC_REQ_CH_7 ((uint32_t)0x00000007)
95 #define HDMA_SRC_REQ_CH_8 ((uint32_t)0x00000008)
96 #define HDMA_SRC_REQ_CH_9 ((uint32_t)0x00000009)
97 #define HDMA_SRC_REQ_CH_10 ((uint32_t)0x0000000A)
98 #define HDMA_SRC_REQ_CH_11 ((uint32_t)0x0000000B)
99 #define HDMA_SRC_REQ_CH_12 ((uint32_t)0x0000000C)
100 #define HDMA_SRC_REQ_CH_13 ((uint32_t)0x0000000D)
101 #define HDMA_SRC_REQ_CH_14 ((uint32_t)0x0000000E)
102 #define HDMA_SRC_REQ_CH_15 ((uint32_t)0x0000000F) /* End of group HDMA_SrcReqCh */
106 
112 #define HDMA_DST_REQ_CH_MEM_USE ((uint32_t)0x00000000)
113 #define HDMA_DST_REQ_CH_1 ((uint32_t)0x00000001)
114 #define HDMA_DST_REQ_CH_2 ((uint32_t)0x00000002)
115 #define HDMA_DST_REQ_CH_3 ((uint32_t)0x00000003)
116 #define HDMA_DST_REQ_CH_4 ((uint32_t)0x00000004)
117 #define HDMA_DST_REQ_CH_5 ((uint32_t)0x00000005)
118 #define HDMA_DST_REQ_CH_6 ((uint32_t)0x00000006)
119 #define HDMA_DST_REQ_CH_7 ((uint32_t)0x00000007)
120 #define HDMA_DST_REQ_CH_8 ((uint32_t)0x00000008)
121 #define HDMA_DST_REQ_CH_9 ((uint32_t)0x00000009)
122 #define HDMA_DST_REQ_CH_10 ((uint32_t)0x0000000A)
123 #define HDMA_DST_REQ_CH_11 ((uint32_t)0x0000000B)
124 #define HDMA_DST_REQ_CH_12 ((uint32_t)0x0000000C)
125 #define HDMA_DST_REQ_CH_13 ((uint32_t)0x0000000D)
126 #define HDMA_DST_REQ_CH_14 ((uint32_t)0x0000000E)
127 #define HDMA_DST_REQ_CH_15 ((uint32_t)0x0000000F) /* End of group HDMA_dstReqCh */
131 
137 #define HDMA_TRANS_INT_COMP_DISABLE ((uint32_t)0x00000000)
138 #define HDMA_TRANS_INT_COMP_ENABLE ((uint32_t)0x80000000) /* End of group HDMA_TransferCompInt */
142 
149 #define HDMA_LLI_ADDRESS_MIN ((uint32_t)0x00000000)
150 #define HDMA_LLI_ADDRESS_MAX ((uint32_t)0x3FFFFFFF) /* End of group HDMA_LliAddress */
154 
161 #define HDMA_TRANS_NUM_RANGE_MIN ((uint32_t)0x00000001)
162 #define HDMA_TRANS_NUM_RANGE_MAX ((uint32_t)0x00000400) /* End of group HDMA_TransferNumRange */
166 
172 #define HDMA_DST_ADDR_FIX ((uint32_t)0x00000000)
173 #define HDMA_DST_ADDR_INC ((uint32_t)0x08000000) /* End of group HDMA_DestinationAddressInc */
177 
183 #define HDMA_SRC_ADDR_FIX ((uint32_t)0x00000000)
184 #define HDMA_SRC_ADDR_INC ((uint32_t)0x04000000) /* End of group HDMA_SourcenAddressInc */
188 
194 #define HDMA_DST_BITWIDTH_1BYTE ((uint32_t)0x00000000)
195 #define HDMA_DST_BITWIDTH_2BYTE ((uint32_t)0x00200000)
196 #define HDMA_DST_BITWIDTH_4BYTE ((uint32_t)0x00400000) /* End of group HDMA_DestinationBitWidth */
200 
206 #define HDMA_DST_BURSTSIZE_1BEAT ((uint32_t)0x00000000)
207 #define HDMA_DST_BURSTSIZE_4BEAT ((uint32_t)0x00008000)
208 #define HDMA_DST_BURSTSIZE_8BEAT ((uint32_t)0x00010000)
209 #define HDMA_DST_BURSTSIZE_16BEAT ((uint32_t)0x00018000)
210 #define HDMA_DST_BURSTSIZE_32BEAT ((uint32_t)0x00020000)
211 #define HDMA_DST_BURSTSIZE_64BEAT ((uint32_t)0x00028000)
212 #define HDMA_DST_BURSTSIZE_128BEAT ((uint32_t)0x00030000)
213 #define HDMA_DST_BURSTSIZE_256BEAT ((uint32_t)0x00038000) /* End of group HDMA_DestinationBurstSize */
217 
223 #define HDMA_SRC_BITWIDTH_1BYTE ((uint32_t)0x00000000)
224 #define HDMA_SRC_BITWIDTH_2BYTE ((uint32_t)0x00040000)
225 #define HDMA_SRC_BITWIDTH_4BYTE ((uint32_t)0x00080000) /* End of group HDMA_SourceBitWidth */
229 
235 #define HDMA_SRC_BURSTSIZE_1BEAT ((uint32_t)0x00000000)
236 #define HDMA_SRC_BURSTSIZE_4BEAT ((uint32_t)0x00001000)
237 #define HDMA_SRC_BURSTSIZE_8BEAT ((uint32_t)0x00002000)
238 #define HDMA_SRC_BURSTSIZE_16BEAT ((uint32_t)0x00003000)
239 #define HDMA_SRC_BURSTSIZE_32BEAT ((uint32_t)0x00004000)
240 #define HDMA_SRC_BURSTSIZE_64BEAT ((uint32_t)0x00005000)
241 #define HDMA_SRC_BURSTSIZE_128BEAT ((uint32_t)0x00006000)
242 #define HDMA_SRC_BURSTSIZE_256BEAT ((uint32_t)0x00007000) /* End of group HDMA_SourceBurstSize */
246 
267 /* E */
273 #define HDMA_CH_E_DISABLE ((uint32_t)0x00000000)
274 #define HDMA_CH_E_ENABLE ((uint32_t)0x00000001) /* End of group HDMAxCnCfg_E */
278 /* SrcPeripheral */
284 #define HDMA_CH_SRCPERI_MASK ((uint32_t)0x0000001E) /* End of group HDMAxCnCfg_SrcPeri */
288 /* FlowCntrl */
294 #define HDMA_CH_FLOWCNT_MEM_MEM ((uint32_t)0x00000000)
295 #define HDMA_CH_FLOWCNT_MEM_PERI ((uint32_t)0x00000800)
296 #define HDMA_CH_FLOWCNT_PERI_MEM ((uint32_t)0x00001000)
297 #define HDMA_CH_FLOWCNT_PERI_PERI ((uint32_t)0x00001800)
298 #define HDMA_CH_FLOWCNT_MASK ((uint32_t)0x00001800) /* End of group HDMAxCnCfg_DstPeri */
302 /* DestPeripheral */
308 #define HDMA_CH_DSTPERI_MASK ((uint32_t)0x000003C0) /* End of group HDMAxCnCfg_DstPeri */
312 /* IE */
318 #define HDMA_CH_IE_DISABLE ((uint32_t)0x00000000)
319 #define HDMA_CH_IE_ENABLE ((uint32_t)0x00004000) /* End of group HDMAxCnCfg_IE */
323 /* ITC */
329 #define HDMA_CH_ITC_DISABLE ((uint32_t)0x00000000)
330 #define HDMA_CH_ITC_ENABLE ((uint32_t)0x00008000) /* End of group HDMAxCnCfg_ITC */
334 /* Lock */
340 #define HDMA_CH_LOCK_DISABLE ((uint32_t)0x00000000)
341 #define HDMA_CH_LOCK_ENABLE ((uint32_t)0x00010000) /* End of group HDMAxCnCfg_LOCK */
345 /* Active */
351 #define HDMA_CH_ACT_MASK ((uint32_t)0x00020000) /* End of group HDMAxCnCfg_ACT */
356 /* Halt */
362 #define HDMA_CH_HALT_ENABLE ((uint32_t)0x00000000)
363 #define HDMA_CH_HALT_DISABLE ((uint32_t)0x00040000) /* End of group HDMAxCnCfg_HALT */
367  /* End of group HDMAxCnCfg*/
370 /* ITC */
376 #define HDMA_ITC_DISABLE ((uint32_t)0x00000000)
377 #define HDMA_ITC_ENABLE ((uint32_t)0x80000000) /* End of group HDMAxCnCnt_ITC */
381  /* End of group HDMA_Exported_define */
384 
385 
386 /*------------------------------------------------------------------------------*/
387 /* Enumerated Type Definition */
388 /*------------------------------------------------------------------------------*/
394 /* no define */
395  /* End of group HDMA_Exported_define */
399 
400 
401 /*------------------------------------------------------------------------------*/
402 /* Structure Definition */
403 /*------------------------------------------------------------------------------*/
409 /*----------------------------------*/
413 /*----------------------------------*/
414 typedef struct
415 {
416  uint32_t srcAdd;
417  uint32_t dstAdd;
419 
420 /*----------------------------------*/
424 /*----------------------------------*/
425 typedef struct
426 {
427  uint32_t dstInc;
429  uint32_t dstSize;
431  uint32_t dstBurstSize;
433  uint32_t srcInc;
435  uint32_t srcSize;
437  uint32_t srcBurstSize;
439  uint32_t transsize;
441  uint32_t lli;
443 } hdma_ch_cnt_t;
444 
445 
446 /*----------------------------------*/
450 /*----------------------------------*/
451 typedef struct
452 {
453  uint32_t halt;
455  uint32_t lock;
457  uint32_t itc;
459  uint32_t ie;
461  uint32_t flowCnt;
463  uint32_t e;
465 } hdma_ch_cfg_t;
466 
467 /*----------------------------------*/
471 /*----------------------------------*/
472 typedef struct
473 {
474  void (*handler)(uint32_t id, TXZ_Result result);
475  uint32_t id;
476  uint32_t type;
477  uint32_t srcReqCh;
478  uint32_t dstReqCh;
484 
485 /*----------------------------------*/
489 /*----------------------------------*/
490 typedef struct hdma_handle
491 {
492  TSB_DMAC_TypeDef *p_instance;
495 } hdma_t;
496  /* End of group HDMA_Exported_typedef */
500 
501 /*------------------------------------------------------------------------------*/
502 /* Functions */
503 /*------------------------------------------------------------------------------*/
508 TXZ_Result hdma_init(hdma_t *p_obj);
510 TXZ_Result hdma_get_error(hdma_t *p_obj, uint32_t *p_err);
513 TXZ_Result hdma_channel_init(hdma_t *p_obj, uint32_t dma_ch);
515 TXZ_Result hdma_HALT_enable(hdma_t *p_obj, uint32_t dma_ch);
516 TXZ_Result hdma_ITC_enable(hdma_t *p_obj, uint32_t dma_ch);
517 TXZ_Result hdma_ITC_disable(hdma_t *p_obj, uint32_t dma_ch);
518 TXZ_Result hdma_LOCK_enable(hdma_t *p_obj, uint32_t dma_ch);
519 TXZ_Result hdma_LOCK_disable(hdma_t *p_obj, uint32_t dma_ch);
520 TXZ_Result hdma_IE_enable(hdma_t *p_obj, uint32_t dma_ch);
521 TXZ_Result hdma_IE_disable(hdma_t *p_obj, uint32_t dma_ch);
522 TXZ_Result hdma_E_enable(hdma_t *p_obj, uint32_t dma_ch);
523 TXZ_Result hdma_E_disable(hdma_t *p_obj, uint32_t dma_ch);
524 TXZ_Result hdma_FlowType_Set(hdma_t *p_obj, uint32_t dma_ch, uint32_t type);
525 TXZ_Result hdma_srcPeri_Set(hdma_t *p_obj, uint32_t dma_ch);
526 TXZ_Result hdma_dstPeri_Set(hdma_t *p_obj, uint32_t dma_ch);
527 TXZ_Result hdma_lli_set(hdma_t *p_obj, uint32_t dma_ch);
528 TXZ_Result hdma_startIt(hdma_t *p_obj, uint32_t dma_ch);
529 TXZ_Result hdma_stopIt(hdma_t *p_obj, uint32_t dma_ch);
530 TXZ_Result hdma_startPeriIt(hdma_t *p_obj, uint32_t dma_ch);
531 TXZ_Result hdma_stopPeriIt(hdma_t *p_obj, uint32_t dma_ch);
532 TXZ_Result get_src_address(hdma_t *p_obj, uint32_t dma_ch, uint32_t *addr);
533 TXZ_Result get_dst_address(hdma_t *p_obj, uint32_t dma_ch, uint32_t *addr);
534  /* End of group HDMA_Exported_functions */
538  /* End of group HDMA */
542  /* End of group Periph_Driver */
546 
547 #ifdef __cplusplus
548 }
549 #endif /* __cplusplus */
550 #endif /* __HDMA_H */
551 
552 
uint32_t dstInc
Definition: txz_hdma.h:427
uint32_t e
Definition: txz_hdma.h:463
uint32_t lock
Definition: txz_hdma.h:455
TXZ_Result hdma_error_irq_handler(hdma_t *p_obj)
TXZ_Result hdma_IE_enable(hdma_t *p_obj, uint32_t dma_ch)
uint32_t dstAdd
Definition: txz_hdma.h:417
TXZ_Result hdma_ITC_enable(hdma_t *p_obj, uint32_t dma_ch)
TXZ_Result hdma_ITC_disable(hdma_t *p_obj, uint32_t dma_ch)
Initial setting structure definition.
Definition: txz_hdma.h:414
uint32_t transsize
Definition: txz_hdma.h:439
TXZ_Result
Definition: txz_driver_def.h:43
uint32_t dstReqCh
Definition: txz_hdma.h:478
uint32_t srcInc
Definition: txz_hdma.h:433
TXZ_Result hdma_lli_set(hdma_t *p_obj, uint32_t dma_ch)
TXZ_Result get_src_address(hdma_t *p_obj, uint32_t dma_ch, uint32_t *addr)
TXZ_Result hdma_FlowType_Set(hdma_t *p_obj, uint32_t dma_ch, uint32_t type)
Channel setting structure definition.
Definition: txz_hdma.h:472
TXZ_Result hdma_IE_disable(hdma_t *p_obj, uint32_t dma_ch)
TSB_DMAC_TypeDef * p_instance
Definition: txz_hdma.h:492
Channel control setting structure definition.
Definition: txz_hdma.h:425
uint32_t dstSize
Definition: txz_hdma.h:429
uint32_t itc
Definition: txz_hdma.h:457
TXZ_Result hdma_stopIt(hdma_t *p_obj, uint32_t dma_ch)
TXZ_Result hdma_irq_handler(hdma_t *p_obj)
uint32_t flowCnt
Definition: txz_hdma.h:461
TXZ_Result hdma_deinit(hdma_t *p_obj)
hdma_ch_cnt_t cnt
Definition: txz_hdma.h:479
TXZ_Result hdma_channel_init(hdma_t *p_obj, uint32_t dma_ch)
hdma_initial_setting_t init
Definition: txz_hdma.h:493
uint32_t dstBurstSize
Definition: txz_hdma.h:431
HDMA handle structure definition.
Definition: txz_hdma.h:490
TXZ_Result hdma_srcPeri_Set(hdma_t *p_obj, uint32_t dma_ch)
TXZ_Result hdma_startIt(hdma_t *p_obj, uint32_t dma_ch)
All common macro and definition for TXZ peripheral drivers.
#define HDMA_CH_NUM
Definition: txz_hdma.h:66
uint32_t halt
Definition: txz_hdma.h:453
TXZ_Result hdma_startPeriIt(hdma_t *p_obj, uint32_t dma_ch)
struct hdma_handle hdma_t
HDMA handle structure definition.
TXZ_Result hdma_E_disable(hdma_t *p_obj, uint32_t dma_ch)
Channel config setting structure definition.
Definition: txz_hdma.h:451
TXZ_Result hdma_get_error(hdma_t *p_obj, uint32_t *p_err)
TXZ_Result hdma_LOCK_disable(hdma_t *p_obj, uint32_t dma_ch)
uint32_t srcReqCh
Definition: txz_hdma.h:477
TXZ_Result hdma_HALT_enable(hdma_t *p_obj, uint32_t dma_ch)
hdma_ch_cfg_t cfg
Definition: txz_hdma.h:481
uint32_t lli
Definition: txz_hdma.h:441
TXZ_Result get_dst_address(hdma_t *p_obj, uint32_t dma_ch, uint32_t *addr)
TXZ_Result hdma_E_enable(hdma_t *p_obj, uint32_t dma_ch)
uint32_t id
Definition: txz_hdma.h:475
uint32_t srcBurstSize
Definition: txz_hdma.h:437
uint32_t type
Definition: txz_hdma.h:476
TXZ_Result hdma_init(hdma_t *p_obj)
TXZ_Result hdma_stopPeriIt(hdma_t *p_obj, uint32_t dma_ch)
uint32_t srcAdd
Definition: txz_hdma.h:416
TXZ_Result hdma_LOCK_enable(hdma_t *p_obj, uint32_t dma_ch)
TXZ_Result hdma_clear_error(hdma_t *p_obj)
TXZ_Result hdma_dstPeri_Set(hdma_t *p_obj, uint32_t dma_ch)
uint32_t srcSize
Definition: txz_hdma.h:435
uint32_t ie
Definition: txz_hdma.h:459
hdma_ch_setting_t ch[HDMA_CH_NUM]
Definition: txz_hdma.h:494