TMPM4G9  V1.0.0.0

Standby Control Register. More...

Macros

#define CGSTBYCR_STBY_RW_IDLE   ((uint32_t)0x00000000)
 
#define CGSTBYCR_STBY_RW_STOP1   ((uint32_t)0x00000001)
 
#define CGSTBYCR_STBY_RW_STOP2   ((uint32_t)0x00000002)
 
#define CGSTBYCR_STBY_RW_IDLE   ((uint32_t)0x00000000)
 
#define CGSTBYCR_STBY_RW_STOP1   ((uint32_t)0x00000001)
 
#define CGSTBYCR_STBY_RW_STOP2   ((uint32_t)0x00000002)
 

Detailed Description

Standby Control Register.

Detail.

Bit Bit Symbol
31:2 -
1:0 STBY

Macro Definition Documentation

§ CGSTBYCR_STBY_RW_IDLE [1/2]

#define CGSTBYCR_STBY_RW_IDLE   ((uint32_t)0x00000000)

STBY :[R/W] :IDLE

§ CGSTBYCR_STBY_RW_IDLE [2/2]

#define CGSTBYCR_STBY_RW_IDLE   ((uint32_t)0x00000000)

STBY :[R/W] :IDLE

§ CGSTBYCR_STBY_RW_STOP1 [1/2]

#define CGSTBYCR_STBY_RW_STOP1   ((uint32_t)0x00000001)

STBY :[R/W] :STOP1

§ CGSTBYCR_STBY_RW_STOP1 [2/2]

#define CGSTBYCR_STBY_RW_STOP1   ((uint32_t)0x00000001)

STBY :[R/W] :STOP1

§ CGSTBYCR_STBY_RW_STOP2 [1/2]

#define CGSTBYCR_STBY_RW_STOP2   ((uint32_t)0x00000002)

STBY :[R/W] :STOP2

§ CGSTBYCR_STBY_RW_STOP2 [2/2]

#define CGSTBYCR_STBY_RW_STOP2   ((uint32_t)0x00000002)

STBY :[R/W] :STOP2