TMPM4G(1) Group Peripheral Driver User Manual
V1.0.0.0
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This file provides all the functions prototypes for UART driver. More...
#include "txz_driver_def.h"
Go to the source code of this file.
Data Structures | |
struct | cec_receive_t |
Receive event information structure definition. More... | |
struct | cec_transmit_t |
Transmit data information structure definition. More... | |
struct | cec_initial_setting_t |
Initial setting structure definition. More... | |
struct | cec_t |
CEC handle structure definition. More... | |
Macros | |
#define | CECxADD_CECADD_0 ((uint32_t)0x00000001) |
#define | CECxADD_CECADD_1 ((uint32_t)0x00000002) |
#define | CECxADD_CECADD_2 ((uint32_t)0x00000004) |
#define | CECxADD_CECADD_3 ((uint32_t)0x00000008) |
#define | CECxADD_CECADD_4 ((uint32_t)0x00000010) |
#define | CECxADD_CECADD_5 ((uint32_t)0x00000020) |
#define | CECxADD_CECADD_6 ((uint32_t)0x00000040) |
#define | CECxADD_CECADD_7 ((uint32_t)0x00000080) |
#define | CECxADD_CECADD_8 ((uint32_t)0x00000100) |
#define | CECxADD_CECADD_9 ((uint32_t)0x00000200) |
#define | CECxADD_CECADD_A ((uint32_t)0x00000400) |
#define | CECxADD_CECADD_B ((uint32_t)0x00000800) |
#define | CECxADD_CECADD_C ((uint32_t)0x00001000) |
#define | CECxADD_CECADD_D ((uint32_t)0x00002000) |
#define | CECxADD_CECADD_E ((uint32_t)0x00004000) |
#define | CECxADD_CECADD_F ((uint32_t)0x00008000) |
#define | CECxRCR1_CECACKDIS_ACK_ON ((uint32_t)0x00000000) |
#define | CECxRCR1_CECACKDIS_ACK_OFF ((uint32_t)0x01000000) |
#define | CECxRCR1_CECHNC_NONE ((uint32_t)0x00000000) |
#define | CECxRCR1_CECHNC_1_FS ((uint32_t)0x00100000) |
#define | CECxRCR1_CECHNC_2_FS ((uint32_t)0x00200000) |
#define | CECxRCR1_CECHNC_3_FS ((uint32_t)0x00300000) |
#define | CECxRCR1_CECLNC_NONE ((uint32_t)0x00000000) |
#define | CECxRCR1_CECLNC_1_FS ((uint32_t)0x00010000) |
#define | CECxRCR1_CECLNC_2_FS ((uint32_t)0x00020000) |
#define | CECxRCR1_CECLNC_3_FS ((uint32_t)0x00030000) |
#define | CECxRCR1_CECMIN_NONE ((uint32_t)0x00000000) |
#define | CECxRCR1_CECMIN_P_1_FS ((uint32_t)0x00001000) |
#define | CECxRCR1_CECMIN_P_2_FS ((uint32_t)0x00002000) |
#define | CECxRCR1_CECMIN_P_3_FS ((uint32_t)0x00003000) |
#define | CECxRCR1_CECMIN_M_1_FS ((uint32_t)0x00004000) |
#define | CECxRCR1_CECMIN_M_2_FS ((uint32_t)0x00005000) |
#define | CECxRCR1_CECMIN_M_3_FS ((uint32_t)0x00006000) |
#define | CECxRCR1_CECMIN_M_4_FS ((uint32_t)0x00007000) |
#define | CECxRCR1_CECMAX_NONE ((uint32_t)0x00000000) |
#define | CECxRCR1_CECMAX_P_1_FS ((uint32_t)0x00000100) |
#define | CECxRCR1_CECMAX_P_2_FS ((uint32_t)0x00000200) |
#define | CECxRCR1_CECMAX_P_3_FS ((uint32_t)0x00000300) |
#define | CECxRCR1_CECMAX_M_1_FS ((uint32_t)0x00000400) |
#define | CECxRCR1_CECMAX_M_2_FS ((uint32_t)0x00000500) |
#define | CECxRCR1_CECMAX_M_3_FS ((uint32_t)0x00000600) |
#define | CECxRCR1_CECMAX_M_4_FS ((uint32_t)0x00000700) |
#define | CECxRCR1_CECDAT_NONE ((uint32_t)0x00000000) |
#define | CECxRCR1_CECDAT_P_2_FS ((uint32_t)0x00000010) |
#define | CECxRCR1_CECDAT_P_4_FS ((uint32_t)0x00000020) |
#define | CECxRCR1_CECDAT_P_6_FS ((uint32_t)0x00000030) |
#define | CECxRCR1_CECDAT_M_2_FS ((uint32_t)0x00000040) |
#define | CECxRCR1_CECDAT_M_4_FS ((uint32_t)0x00000050) |
#define | CECxRCR1_CECDAT_M_6_FS ((uint32_t)0x00000060) |
#define | CECxRCR1_CECTOUT_1BIT ((uint32_t)0x00000000) |
#define | CECxRCR1_CECTOUT_2BIT ((uint32_t)0x00000004) |
#define | CECxRCR1_CECTOUT_3BIT ((uint32_t)0x00000008) |
#define | CECxRCR1_CECRIHLD_OFF ((uint32_t)0x00000000) |
#define | CECxRCR1_CECRIHLD_ON ((uint32_t)0x00000002) |
#define | CECxRCR1_CECOTH_OFF ((uint32_t)0x00000000) |
#define | CECxRCR1_CECOTH_ON ((uint32_t)0x00000001) |
#define | CECxRCR2_CECSWAV3_NONE ((uint32_t)0x00000000) |
#define | CECxRCR2_CECSWAV3_1_FS ((uint32_t)0x00001000) |
#define | CECxRCR2_CECSWAV3_2_FS ((uint32_t)0x00002000) |
#define | CECxRCR2_CECSWAV3_3_FS ((uint32_t)0x00003000) |
#define | CECxRCR2_CECSWAV3_4_FS ((uint32_t)0x00004000) |
#define | CECxRCR2_CECSWAV3_5_FS ((uint32_t)0x00005000) |
#define | CECxRCR2_CECSWAV3_6_FS ((uint32_t)0x00006000) |
#define | CECxRCR2_CECSWAV3_7_FS ((uint32_t)0x00007000) |
#define | CECxRCR2_CECSWAV2_NONE ((uint32_t)0x00000000) |
#define | CECxRCR2_CECSWAV2_1_FS ((uint32_t)0x00000100) |
#define | CECxRCR2_CECSWAV2_2_FS ((uint32_t)0x00000200) |
#define | CECxRCR2_CECSWAV2_3_FS ((uint32_t)0x00000300) |
#define | CECxRCR2_CECSWAV2_4_FS ((uint32_t)0x00000400) |
#define | CECxRCR2_CECSWAV2_5_FS ((uint32_t)0x00000500) |
#define | CECxRCR2_CECSWAV2_6_FS ((uint32_t)0x00000600) |
#define | CECxRCR2_CECSWAV2_7_FS ((uint32_t)0x00000700) |
#define | CECxRCR2_CECSWAV1_NONE ((uint32_t)0x00000000) |
#define | CECxRCR2_CECSWAV1_1_FS ((uint32_t)0x00000010) |
#define | CECxRCR2_CECSWAV1_2_FS ((uint32_t)0x00000020) |
#define | CECxRCR2_CECSWAV1_3_FS ((uint32_t)0x00000030) |
#define | CECxRCR2_CECSWAV1_4_FS ((uint32_t)0x00000040) |
#define | CECxRCR2_CECSWAV1_5_FS ((uint32_t)0x00000050) |
#define | CECxRCR2_CECSWAV1_6_FS ((uint32_t)0x00000060) |
#define | CECxRCR2_CECSWAV1_7_FS ((uint32_t)0x00000070) |
#define | CECxRCR2_CECSWAV0_NONE ((uint32_t)0x00000000) |
#define | CECxRCR2_CECSWAV0_1_FS ((uint32_t)0x00000001) |
#define | CECxRCR2_CECSWAV0_2_FS ((uint32_t)0x00000002) |
#define | CECxRCR2_CECSWAV0_3_FS ((uint32_t)0x00000003) |
#define | CECxRCR2_CECSWAV0_4_FS ((uint32_t)0x00000004) |
#define | CECxRCR2_CECSWAV0_5_FS ((uint32_t)0x00000005) |
#define | CECxRCR2_CECSWAV0_6_FS ((uint32_t)0x00000006) |
#define | CECxRCR2_CECSWAV0_7_FS ((uint32_t)0x00000007) |
#define | CECxRCR3_CECWAV3_NONE ((uint32_t)0x00000000) |
#define | CECxRCR3_CECWAV3_1_FS ((uint32_t)0x00100000) |
#define | CECxRCR3_CECWAV3_2_FS ((uint32_t)0x00200000) |
#define | CECxRCR3_CECWAV3_3_FS ((uint32_t)0x00300000) |
#define | CECxRCR3_CECWAV3_4_FS ((uint32_t)0x00400000) |
#define | CECxRCR3_CECWAV3_5_FS ((uint32_t)0x00500000) |
#define | CECxRCR3_CECWAV3_6_FS ((uint32_t)0x00600000) |
#define | CECxRCR3_CECWAV3_7_FS ((uint32_t)0x00700000) |
#define | CECxRCR3_CECWAV2_NONE ((uint32_t)0x00000000) |
#define | CECxRCR3_CECWAV2_1_FS ((uint32_t)0x00010000) |
#define | CECxRCR3_CECWAV2_2_FS ((uint32_t)0x00020000) |
#define | CECxRCR3_CECWAV2_3_FS ((uint32_t)0x00030000) |
#define | CECxRCR3_CECWAV2_4_FS ((uint32_t)0x00040000) |
#define | CECxRCR3_CECWAV2_5_FS ((uint32_t)0x00050000) |
#define | CECxRCR3_CECWAV2_6_FS ((uint32_t)0x00060000) |
#define | CECxRCR3_CECWAV2_7_FS ((uint32_t)0x00070000) |
#define | CECxRCR3_CECWAV1_NONE ((uint32_t)0x00000000) |
#define | CECxRCR3_CECWAV1_1_FS ((uint32_t)0x00001000) |
#define | CECxRCR3_CECWAV1_2_FS ((uint32_t)0x00002000) |
#define | CECxRCR3_CECWAV1_3_FS ((uint32_t)0x00003000) |
#define | CECxRCR3_CECWAV1_4_FS ((uint32_t)0x00004000) |
#define | CECxRCR3_CECWAV1_5_FS ((uint32_t)0x00005000) |
#define | CECxRCR3_CECWAV1_6_FS ((uint32_t)0x00006000) |
#define | CECxRCR3_CECWAV1_7_FS ((uint32_t)0x00007000) |
#define | CECxRCR3_CECWAV0_NONE ((uint32_t)0x00000000) |
#define | CECxRCR3_CECWAV0_1_FS ((uint32_t)0x00000100) |
#define | CECxRCR3_CECWAV0_2_FS ((uint32_t)0x00000200) |
#define | CECxRCR3_CECWAV0_3_FS ((uint32_t)0x00000300) |
#define | CECxRCR3_CECWAV0_4_FS ((uint32_t)0x00000400) |
#define | CECxRCR3_CECWAV0_5_FS ((uint32_t)0x00000500) |
#define | CECxRCR3_CECWAV0_6_FS ((uint32_t)0x00000600) |
#define | CECxRCR3_CECWAV0_7_FS ((uint32_t)0x00000700) |
#define | CECxRCR3_CECRSTAEN_DISABLE ((uint32_t)0x00000000) |
#define | CECxRCR3_CECRSTAEN_ENABLE ((uint32_t)0x00000002) |
#define | CECxRCR3_CECWAVEN_DISABLE ((uint32_t)0x00000000) |
#define | CECxRCR3_CECWAVEN_ENABLE ((uint32_t)0x00000001) |
#define | CECxTCR_CECSTRS_NONE ((uint32_t)0x00000000) |
#define | CECxTCR_CECSTRS_1_FS ((uint32_t)0x00100000) |
#define | CECxTCR_CECSTRS_2_FS ((uint32_t)0x00200000) |
#define | CECxTCR_CECSTRS_3_FS ((uint32_t)0x00300000) |
#define | CECxTCR_CECSTRS_4_FS ((uint32_t)0x00400000) |
#define | CECxTCR_CECSTRS_5_FS ((uint32_t)0x00500000) |
#define | CECxTCR_CECSTRS_6_FS ((uint32_t)0x00600000) |
#define | CECxTCR_CECSTRS_7_FS ((uint32_t)0x00700000) |
#define | CECxTCR_CECSPRD_NONE ((uint32_t)0x00000000) |
#define | CECxTCR_CECSPRD_1_FS ((uint32_t)0x00010000) |
#define | CECxTCR_CECSPRD_2_FS ((uint32_t)0x00020000) |
#define | CECxTCR_CECSPRD_3_FS ((uint32_t)0x00030000) |
#define | CECxTCR_CECSPRD_4_FS ((uint32_t)0x00040000) |
#define | CECxTCR_CECSPRD_5_FS ((uint32_t)0x00050000) |
#define | CECxTCR_CECSPRD_6_FS ((uint32_t)0x00060000) |
#define | CECxTCR_CECSPRD_7_FS ((uint32_t)0x00070000) |
#define | CECxTCR_CECDTRS_NONE ((uint32_t)0x00000000) |
#define | CECxTCR_CECDTRS_1_FS ((uint32_t)0x00001000) |
#define | CECxTCR_CECDTRS_2_FS ((uint32_t)0x00002000) |
#define | CECxTCR_CECDTRS_3_FS ((uint32_t)0x00003000) |
#define | CECxTCR_CECDPRD_NONE ((uint32_t)0x00000000) |
#define | CECxTCR_CECDPRD_1_FS ((uint32_t)0x00000100) |
#define | CECxTCR_CECDPRD_2_FS ((uint32_t)0x00000200) |
#define | CECxTCR_CECDPRD_3_FS ((uint32_t)0x00000300) |
#define | CECxTCR_CECDPRD_4_FS ((uint32_t)0x00000400) |
#define | CECxTCR_CECDPRD_5_FS ((uint32_t)0x00000500) |
#define | CECxTCR_CECDPRD_6_FS ((uint32_t)0x00000600) |
#define | CECxTCR_CECDPRD_7_FS ((uint32_t)0x00000700) |
#define | CECxTCR_CECDPRD_8_FS ((uint32_t)0x00000800) |
#define | CECxTCR_CECDPRD_9_FS ((uint32_t)0x00000900) |
#define | CECxTCR_CECDPRD_10_FS ((uint32_t)0x00000A00) |
#define | CECxTCR_CECDPRD_11_FS ((uint32_t)0x00000B00) |
#define | CECxTCR_CECDPRD_12_FS ((uint32_t)0x00000C00) |
#define | CECxTCR_CECDPRD_13_FS ((uint32_t)0x00000D00) |
#define | CECxTCR_CECDPRD_14_FS ((uint32_t)0x00000E00) |
#define | CECxTCR_CECDPRD_15_FS ((uint32_t)0x00000F00) |
#define | CECxTCR_CECBRD_OFF ((uint32_t)0x00000000) |
#define | CECxTCR_CECBRD_ON ((uint32_t)0x00000010) |
#define | CECxTCR_CECFREE_NONE ((uint32_t)0x00000000) |
#define | CECxTCR_CECFREE_1_BIT ((uint32_t)0x00000001) |
#define | CECxTCR_CECFREE_2_BIT ((uint32_t)0x00000002) |
#define | CECxTCR_CECFREE_3_BIT ((uint32_t)0x00000003) |
#define | CECxTCR_CECFREE_4_BIT ((uint32_t)0x00000004) |
#define | CECxTCR_CECFREE_5_BIT ((uint32_t)0x00000005) |
#define | CECxTCR_CECFREE_6_BIT ((uint32_t)0x00000006) |
#define | CECxTCR_CECFREE_7_BIT ((uint32_t)0x00000007) |
#define | CECxTCR_CECFREE_8_BIT ((uint32_t)0x00000008) |
#define | CECxTCR_CECFREE_9_BIT ((uint32_t)0x00000009) |
#define | CECxTCR_CECFREE_10_BIT ((uint32_t)0x0000000A) |
#define | CECxTCR_CECFREE_11_BIT ((uint32_t)0x0000000B) |
#define | CECxTCR_CECFREE_12_BIT ((uint32_t)0x0000000C) |
#define | CECxTCR_CECFREE_13_BIT ((uint32_t)0x0000000D) |
#define | CECxTCR_CECFREE_14_BIT ((uint32_t)0x0000000E) |
#define | CECxTCR_CECFREE_15_BIT ((uint32_t)0x0000000F) |
#define | CECxRSTAT_CECRIBFOV_MASK ((uint32_t)0x80000000) |
#define | CECxRSTAT_CECRIBFOV_CLR ((uint32_t)0x00000000) |
#define | CECxRSTAT_CECRIBFOV_SET ((uint32_t)0x80000000) |
#define | CECxRSTAT_CECRIWAV_MASK ((uint32_t)0x00000040) |
#define | CECxRSTAT_CECRIWAV_CLR ((uint32_t)0x00000000) |
#define | CECxRSTAT_CECRIWAV_SET ((uint32_t)0x00000040) |
#define | CECxRSTAT_CECRIOR_MASK ((uint32_t)0x00000020) |
#define | CECxRSTAT_CECRIOR_CLR ((uint32_t)0x00000000) |
#define | CECxRSTAT_CECRIOR_SET ((uint32_t)0x00000020) |
#define | CECxRSTAT_CECRIACK_MASK ((uint32_t)0x00000010) |
#define | CECxRSTAT_CECRIACK_CLR ((uint32_t)0x00000000) |
#define | CECxRSTAT_CECRIACK_SET ((uint32_t)0x00000010) |
#define | CECxRSTAT_CECRIMIN_MASK ((uint32_t)0x00000008) |
#define | CECxRSTAT_CECRIMIN_CLR ((uint32_t)0x00000000) |
#define | CECxRSTAT_CECRIMIN_SET ((uint32_t)0x00000008) |
#define | CECxRSTAT_CECRIMAX_MASK ((uint32_t)0x00000004) |
#define | CECxRSTAT_CECRIMAX_CLR ((uint32_t)0x00000000) |
#define | CECxRSTAT_CECRIMAX_SET ((uint32_t)0x00000004) |
#define | CECxRSTAT_CECRISTA_MASK ((uint32_t)0x00000002) |
#define | CECxRSTAT_CECRISTA_CLR ((uint32_t)0x00000000) |
#define | CECxRSTAT_CECRISTA_SET ((uint32_t)0x00000002) |
#define | CECxRSTAT_CECRIEND_MASK ((uint32_t)0x00000001) |
#define | CECxRSTAT_CECRIEND_CLR ((uint32_t)0x00000000) |
#define | CECxRSTAT_CECRIEND_SET ((uint32_t)0x00000001) |
#define | CECxTSTAT_CECTIUR_MASK ((uint32_t)0x00000010) |
#define | CECxTSTAT_CECTIUR_CLR ((uint32_t)0x00000000) |
#define | CECxTSTAT_CECTIUR_SET ((uint32_t)0x00000010) |
#define | CECxTSTAT_CECTIACK_MASK ((uint32_t)0x00000008) |
#define | CECxTSTAT_CECTIACK_CLR ((uint32_t)0x00000000) |
#define | CECxTSTAT_CECTIACK_SET ((uint32_t)0x00000008) |
#define | CECxTSTAT_CECTIAL_MASK ((uint32_t)0x00000004) |
#define | CECxTSTAT_CECTIAL_CLR ((uint32_t)0x00000000) |
#define | CECxTSTAT_CECTIAL_SET ((uint32_t)0x00000004) |
#define | CECxTSTAT_CECTIEND_MASK ((uint32_t)0x00000002) |
#define | CECxTSTAT_CECTIEND_CLR ((uint32_t)0x00000000) |
#define | CECxTSTAT_CECTIEND_SET ((uint32_t)0x00000002) |
#define | CECxTSTAT_CECTISTA_MASK ((uint32_t)0x00000001) |
#define | CECxTSTAT_CECTISTA_CLR ((uint32_t)0x00000000) |
#define | CECxTSTAT_CECTISTA_SET ((uint32_t)0x00000001) |
#define | CECxFSSEL_CECCLK_FS ((uint32_t)0x00000000) |
#define | CECxFSSEL_CECCLK_TBXOUT ((uint32_t)0x00000001) |
Functions | |
TXZ_Result | cec_init (cec_t *p_obj) |
TXZ_Result | cec_deinit (cec_t *p_obj) |
TXZ_Result | cec_discard_transmit (cec_t *p_obj) |
TXZ_Result | cec_discard_receive (cec_t *p_obj) |
TXZ_Result | cec_transmitIt (cec_t *p_obj, cec_transmit_t *p_info) |
TXZ_Result | cec_receiveIt (cec_t *p_obj, cec_receive_t *p_info) |
void | cec_transmit_irq_handler (cec_t *p_obj) |
void | cec_receive_irq_handler (cec_t *p_obj) |
TXZ_Result | cec_get_tx_status (cec_t *p_obj, uint32_t *p_tx_status) |
TXZ_Result | cec_get_rx_status (cec_t *p_obj, uint32_t *p_rx_status) |
This file provides all the functions prototypes for UART driver.
DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
Copyright(C) Toshiba Electronic Device Solutions Corporation 2019