TMPM4G9  V1.0.0.0

#include <TMPM4G6.h>

Data Fields

__IO uint32_t MDEN
 
__IO uint32_t PORTMD
 
__IO uint32_t MDCR
 
__I uint32_t CARSTA
 
__I uint32_t BCARI
 
__IO uint32_t RATE
 
__IO uint32_t CMPU
 
__IO uint32_t CMPV
 
__IO uint32_t CMPW
 
__IO uint32_t MODESEL
 
__IO uint32_t MDOUT
 
__IO uint32_t MDPOT
 
__O uint32_t EMGREL
 
__IO uint32_t EMGCR
 
__I uint32_t EMGSTA
 
__IO uint32_t OVVCR
 
__I uint32_t OVVSTA
 
__IO uint32_t DTR
 
__IO uint32_t TRGCMP0
 
__IO uint32_t TRGCMP1
 
__IO uint32_t TRGCMP2
 
__IO uint32_t TRGCMP3
 
__IO uint32_t TRGCR
 
__IO uint32_t TRGMD
 
__IO uint32_t TRGSEL
 
__IO uint32_t TRGSYNCR
 
__IO uint32_t VPWMPH
 
__IO uint32_t WPWMPH
 
__IO uint32_t MBUFCR
 
__IO uint32_t SYNCCR
 

Field Documentation

§ BCARI

__I uint32_t BCARI

PWM Basic Carrier Register

§ CARSTA

__I uint32_t CARSTA

PWM Carrier Status Register

§ CMPU

__IO uint32_t CMPU

PMD PWM Compare U Register

§ CMPV

__IO uint32_t CMPV

PMD PWM Compare V Register

§ CMPW

__IO uint32_t CMPW

PMD PWM Compare W Register

§ DTR

__IO uint32_t DTR

PMD Dead Time Register

§ EMGCR

__IO uint32_t EMGCR

PMD EMG Control Register

§ EMGREL

__O uint32_t EMGREL

PMD EMG Release Register

§ EMGSTA

__I uint32_t EMGSTA

PMD EMG Status Register

§ MBUFCR

__IO uint32_t MBUFCR

Update timing of the triple buffer

§ MDCR

__IO uint32_t MDCR

PMD Control Register

§ MDEN

__IO uint32_t MDEN

PMD Enable Register

§ MDOUT

__IO uint32_t MDOUT

PMD Conduction Control Register

§ MDPOT

__IO uint32_t MDPOT

PMD Output Setting Register

§ MODESEL

__IO uint32_t MODESEL

PMD Mode Select Register

§ OVVCR

__IO uint32_t OVVCR

PMD OVV Control Register

§ OVVSTA

__I uint32_t OVVSTA

PMD OVV Status Register

§ PORTMD

__IO uint32_t PORTMD

PMD Port Output Mode Register

§ RATE

__IO uint32_t RATE

PWM Frequency Register

§ SYNCCR

__IO uint32_t SYNCCR

Synchronization control between the PMD channel

§ TRGCMP0

__IO uint32_t TRGCMP0

PMD Trigger Compare Register 0

§ TRGCMP1

__IO uint32_t TRGCMP1

PMD Trigger Compare Register 1

§ TRGCMP2

__IO uint32_t TRGCMP2

PMD Trigger Compare Register 2

§ TRGCMP3

__IO uint32_t TRGCMP3

PMD Trigger Compare Register 3

§ TRGCR

__IO uint32_t TRGCR

PMD Trigger Control Register

§ TRGMD

__IO uint32_t TRGMD

PMD Trigger Output Mode Setting Register

§ TRGSEL

__IO uint32_t TRGSEL

PMD Trigger Output Select Register

§ TRGSYNCR

__IO uint32_t TRGSYNCR

PMD Trigger Update Timing Setting Register

§ VPWMPH

__IO uint32_t VPWMPH

Phase difference setting of the V-phase PWM

§ WPWMPH

__IO uint32_t WPWMPH

Phase difference setting of the W-phase PWM


The documentation for this struct was generated from the following files: