TMPM4G9
V1.0.0.0
|
CG Control Register. More...
Macros | |
#define | CGOSCCR_IHOSC2F_MASK ((uint32_t)0x00080000) |
#define | CGOSCCR_IHOSC2F_R_STOP ((uint32_t)0x00000000) |
#define | CGOSCCR_IHOSC2F_R_RUNNING ((uint32_t)0x00080000) |
#define | CGOSCCR_OSCF_MASK ((uint32_t)0x00000200) |
#define | CGOSCCR_OSCF_R_IHOSC ((uint32_t)0x00000000) |
#define | CGOSCCR_OSCF_R_EHOSC ((uint32_t)0x00000200) |
#define | CGOSCCR_OSCSEL_MASK ((uint32_t)0x00000100) |
#define | CGOSCCR_OSCSEL_RW_IHOSC ((uint32_t)0x00000000) |
#define | CGOSCCR_OSCSEL_RW_EHOSC ((uint32_t)0x00000100) |
#define | CGOSCCR_IHOSC2EN_MASK ((uint32_t)0x00000008) |
#define | CGOSCCR_IHOSC2EN_RW_DISABLE ((uint32_t)0x00000000) |
#define | CGOSCCR_IHOSC2EN_RW_ENABLE ((uint32_t)0x00000008) |
#define | CGOSCCR_EOSCEN_MASK ((uint32_t)0x00000006) |
#define | CGOSCCR_EOSCEN_RW_UNUSE ((uint32_t)0x00000000) |
#define | CGOSCCR_EOSCEN_RW_EHOSC ((uint32_t)0x00000002) |
#define | CGOSCCR_EOSCEN_RW_ECLK ((uint32_t)0x00000004) |
#define | CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) |
#define | CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) |
#define | CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) |
#define | CGOSCCR_IHOSC2F_MASK ((uint32_t)0x00080000) |
#define | CGOSCCR_IHOSC2F_R_STOP ((uint32_t)0x00000000) |
#define | CGOSCCR_IHOSC2F_R_RUNNING ((uint32_t)0x00080000) |
#define | CGOSCCR_OSCF_MASK ((uint32_t)0x00000200) |
#define | CGOSCCR_OSCF_R_IHOSC ((uint32_t)0x00000000) |
#define | CGOSCCR_OSCF_R_EHOSC ((uint32_t)0x00000200) |
#define | CGOSCCR_OSCSEL_MASK ((uint32_t)0x00000100) |
#define | CGOSCCR_OSCSEL_RW_IHOSC ((uint32_t)0x00000000) |
#define | CGOSCCR_OSCSEL_RW_EHOSC ((uint32_t)0x00000100) |
#define | CGOSCCR_IHOSC2EN_MASK ((uint32_t)0x00000008) |
#define | CGOSCCR_IHOSC2EN_RW_DISABLE ((uint32_t)0x00000000) |
#define | CGOSCCR_IHOSC2EN_RW_ENABLE ((uint32_t)0x00000008) |
#define | CGOSCCR_EOSCEN_MASK ((uint32_t)0x00000006) |
#define | CGOSCCR_EOSCEN_RW_UNUSE ((uint32_t)0x00000000) |
#define | CGOSCCR_EOSCEN_RW_EHOSC ((uint32_t)0x00000002) |
#define | CGOSCCR_EOSCEN_RW_ECLK ((uint32_t)0x00000004) |
#define | CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) |
#define | CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) |
#define | CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) |
CG Control Register.
Detail.
Bit | Bit Symbol |
---|---|
31:20 | - |
19 | IHOSC2F |
18:17 | - |
16 | IHOSC1F |
15:10 | - |
9 | OSCF |
8 | OSCSEL |
7:4 | - |
3 | IHOSC2EN |
2:1 | EOSCEN |
0 | IHOSC1EN |
#define CGOSCCR_EOSCEN_MASK ((uint32_t)0x00000006) |
EOSCEN :Mask
#define CGOSCCR_EOSCEN_MASK ((uint32_t)0x00000006) |
EOSCEN :Mask
#define CGOSCCR_EOSCEN_RW_ECLK ((uint32_t)0x00000004) |
EOSCEN :[R/W] :External Clock
#define CGOSCCR_EOSCEN_RW_ECLK ((uint32_t)0x00000004) |
EOSCEN :[R/W] :External Clock
#define CGOSCCR_EOSCEN_RW_EHOSC ((uint32_t)0x00000002) |
EOSCEN :[R/W] :External HOSC
#define CGOSCCR_EOSCEN_RW_EHOSC ((uint32_t)0x00000002) |
EOSCEN :[R/W] :External HOSC
#define CGOSCCR_EOSCEN_RW_UNUSE ((uint32_t)0x00000000) |
EOSCEN :[R/W] :Unuse
#define CGOSCCR_EOSCEN_RW_UNUSE ((uint32_t)0x00000000) |
EOSCEN :[R/W] :Unuse
#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) |
IHOSC1EN :Mask
#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) |
IHOSC1EN :Mask
#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) |
IHOSC1EN :[R/W] :Disable
#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) |
IHOSC1EN :[R/W] :Disable
#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) |
IHOSC1EN :[R/W] :Enable
#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) |
IHOSC1EN :[R/W] :Enable
#define CGOSCCR_IHOSC2EN_MASK ((uint32_t)0x00000008) |
IHOSC2EN :Mask
#define CGOSCCR_IHOSC2EN_MASK ((uint32_t)0x00000008) |
IHOSC2EN :Mask
#define CGOSCCR_IHOSC2EN_RW_DISABLE ((uint32_t)0x00000000) |
IHOSC2EN :[R/W] :Disable
#define CGOSCCR_IHOSC2EN_RW_DISABLE ((uint32_t)0x00000000) |
IHOSC2EN :[R/W] :Disable
#define CGOSCCR_IHOSC2EN_RW_ENABLE ((uint32_t)0x00000008) |
IHOSC2EN :[R/W] :Enable
#define CGOSCCR_IHOSC2EN_RW_ENABLE ((uint32_t)0x00000008) |
IHOSC2EN :[R/W] :Enable
#define CGOSCCR_IHOSC2F_MASK ((uint32_t)0x00080000) |
IHOSC2F :Mask
#define CGOSCCR_IHOSC2F_MASK ((uint32_t)0x00080000) |
IHOSC2F :Mask
#define CGOSCCR_IHOSC2F_R_RUNNING ((uint32_t)0x00080000) |
IHOSC2F :[R] :Running
#define CGOSCCR_IHOSC2F_R_RUNNING ((uint32_t)0x00080000) |
IHOSC2F :[R] :Running
#define CGOSCCR_IHOSC2F_R_STOP ((uint32_t)0x00000000) |
IHOSC2F :[R] :Stop
#define CGOSCCR_IHOSC2F_R_STOP ((uint32_t)0x00000000) |
IHOSC2F :[R] :Stop
#define CGOSCCR_OSCF_MASK ((uint32_t)0x00000200) |
OSCF :Mask
#define CGOSCCR_OSCF_MASK ((uint32_t)0x00000200) |
OSCF :Mask
#define CGOSCCR_OSCF_R_EHOSC ((uint32_t)0x00000200) |
OSCF :[R] :External HOSC
#define CGOSCCR_OSCF_R_EHOSC ((uint32_t)0x00000200) |
OSCF :[R] :External HOSC
#define CGOSCCR_OSCF_R_IHOSC ((uint32_t)0x00000000) |
OSCF :[R] :Internal HOSC
#define CGOSCCR_OSCF_R_IHOSC ((uint32_t)0x00000000) |
OSCF :[R] :Internal HOSC
#define CGOSCCR_OSCSEL_MASK ((uint32_t)0x00000100) |
OSCSEL :Mask
#define CGOSCCR_OSCSEL_MASK ((uint32_t)0x00000100) |
OSCSEL :Mask
#define CGOSCCR_OSCSEL_RW_EHOSC ((uint32_t)0x00000100) |
OSCSEL :[R/W] :External HOSC
#define CGOSCCR_OSCSEL_RW_EHOSC ((uint32_t)0x00000100) |
OSCSEL :[R/W] :External HOSC
#define CGOSCCR_OSCSEL_RW_IHOSC ((uint32_t)0x00000000) |
OSCSEL :[R/W] :Internal HOSC
#define CGOSCCR_OSCSEL_RW_IHOSC ((uint32_t)0x00000000) |
OSCSEL :[R/W] :Internal HOSC