ARM Prime Cell PL011.
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#include <TMPM4G6.h>
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__IO uint32_t | DR |
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union { |
__I uint32_t RSR |
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__O uint32_t ECR |
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}; | |
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uint32_t | RESERVED0 [4] |
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__I uint32_t | FR |
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uint32_t | RESERVED1 |
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__IO uint32_t | ILPR |
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__IO uint32_t | BRD |
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__IO uint32_t | FBRD |
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__IO uint32_t | LCR_H |
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__IO uint32_t | CR |
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__IO uint32_t | IFLS |
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__IO uint32_t | IMSC |
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__I uint32_t | RIS |
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__I uint32_t | MIS |
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__O uint32_t | ICR |
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__IO uint32_t | DMACR |
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union { |
__I uint32_t RSR |
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__O uint32_t ECR |
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}; | |
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union { |
__I uint32_t RSR |
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__O uint32_t ECR |
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}; | |
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union { |
__I uint32_t RSR |
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__O uint32_t ECR |
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}; | |
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§ @1
§ @13
§ @5
§ @9
§ BRD
Integer Baud Rate Register
§ CR
§ DMACR
§ DR
§ ECR
§ FBRD
Fractional Baud Rate Register
§ FR
§ ICR
§ IFLS
Interrupt FIFO Level Select Register
§ ILPR
IrDA Low-power Counter register
§ IMSC
Interrupt Mask set/Clear Register
§ LCR_H
§ MIS
Masked Interrupt Status Register
§ RESERVED0
§ RESERVED1
§ RIS
Raw Interrupt Status Register
§ RSR
The documentation for this struct was generated from the following files:
- C:/W_JOB(TOSHIBA)/TMPM4G9/release/TMPM4G9_release_20190424/TMPM4G9_V1000/Libraries/CMSIS/TMPM4G6.h
- C:/W_JOB(TOSHIBA)/TMPM4G9/release/TMPM4G9_release_20190424/TMPM4G9_V1000/Libraries/CMSIS/TMPM4G7.h
- C:/W_JOB(TOSHIBA)/TMPM4G9/release/TMPM4G9_release_20190424/TMPM4G9_V1000/Libraries/CMSIS/TMPM4G8.h
- C:/W_JOB(TOSHIBA)/TMPM4G9/release/TMPM4G9_release_20190424/TMPM4G9_V1000/Libraries/CMSIS/TMPM4G9.h