TMPM4G9  V1.0.0.0

Interrupt control A Register. More...

#include <TMPM4G6.h>

Data Fields

__IO uint8_t NIC00
 
uint8_t RESERVED0 [31]
 
__IO uint8_t IMC00
 
__IO uint8_t IMC01
 
__IO uint8_t IMC02
 
__IO uint8_t IMC03
 
__IO uint8_t IMC04
 
__IO uint8_t IMC05
 
__IO uint8_t IMC06
 
__IO uint8_t IMC07
 
__IO uint8_t IMC08
 
__IO uint8_t IMC09
 
__IO uint8_t IMC10
 
__IO uint8_t IMC11
 
__IO uint8_t IMC12
 
__IO uint8_t IMC13
 
__IO uint8_t IMC14
 
__IO uint8_t IMC15
 
__IO uint8_t IMC16
 
__IO uint8_t IMC17
 
__IO uint8_t IMC18
 
__IO uint8_t IMC19
 
__IO uint8_t IMC20
 
__IO uint8_t IMC21
 
__IO uint8_t IMC22
 
__IO uint8_t IMC23
 
uint8_t RESERVED1 [25]
 
__IO uint8_t IMC49
 
__IO uint8_t IMC50
 
__IO uint8_t IMC51
 
__IO uint8_t IMC52
 
uint8_t RESERVED2 [2]
 
__IO uint8_t IMC55
 
uint8_t RESERVED3
 
__IO uint8_t IMC57
 
__IO uint8_t IMC24
 
__IO uint8_t IMC25
 
__IO uint8_t IMC26
 
__IO uint8_t IMC27
 
__IO uint8_t IMC53
 
__IO uint8_t IMC56
 
__IO uint8_t IMC28
 
__IO uint8_t IMC29
 
__IO uint8_t IMC30
 
__IO uint8_t IMC31
 
__IO uint8_t IMC54
 

Detailed Description

Interrupt control A Register.

Field Documentation

§ IMC00

__IO uint8_t IMC00

interrupt Mode Control Register A 00

§ IMC01

__IO uint8_t IMC01

interrupt Mode Control Register A 01

§ IMC02

__IO uint8_t IMC02

interrupt Mode Control Register A 02

§ IMC03

__IO uint8_t IMC03

interrupt Mode Control Register A 03

§ IMC04

__IO uint8_t IMC04

interrupt Mode Control Register A 04

§ IMC05

__IO uint8_t IMC05

interrupt Mode Control Register A 05

§ IMC06

__IO uint8_t IMC06

interrupt Mode Control Register A 06

§ IMC07

__IO uint8_t IMC07

interrupt Mode Control Register A 07

§ IMC08

__IO uint8_t IMC08

interrupt Mode Control Register A 08

§ IMC09

__IO uint8_t IMC09

interrupt Mode Control Register A 09

§ IMC10

__IO uint8_t IMC10

interrupt Mode Control Register A 10

§ IMC11

__IO uint8_t IMC11

interrupt Mode Control Register A 11

§ IMC12

__IO uint8_t IMC12

interrupt Mode Control Register A 12

§ IMC13

__IO uint8_t IMC13

interrupt Mode Control Register A 13

§ IMC14

__IO uint8_t IMC14

interrupt Mode Control Register A 14

§ IMC15

__IO uint8_t IMC15

interrupt Mode Control Register A 15

§ IMC16

__IO uint8_t IMC16

interrupt Mode Control Register A 16

§ IMC17

__IO uint8_t IMC17

interrupt Mode Control Register A 17

§ IMC18

__IO uint8_t IMC18

interrupt Mode Control Register A 18

§ IMC19

__IO uint8_t IMC19

interrupt Mode Control Register A 19

§ IMC20

__IO uint8_t IMC20

interrupt Mode Control Register A 20

§ IMC21

__IO uint8_t IMC21

interrupt Mode Control Register A 21

§ IMC22

__IO uint8_t IMC22

interrupt Mode Control Register A 22

§ IMC23

__IO uint8_t IMC23

interrupt Mode Control Register A 23

§ IMC24

__IO uint8_t IMC24

interrupt Mode Control Register A 24

§ IMC25

__IO uint8_t IMC25

interrupt Mode Control Register A 25

§ IMC26

__IO uint8_t IMC26

interrupt Mode Control Register A 26

§ IMC27

__IO uint8_t IMC27

interrupt Mode Control Register A 27

§ IMC28

__IO uint8_t IMC28

interrupt Mode Control Register A 28

§ IMC29

__IO uint8_t IMC29

interrupt Mode Control Register A 29

§ IMC30

__IO uint8_t IMC30

interrupt Mode Control Register A 30

§ IMC31

__IO uint8_t IMC31

interrupt Mode Control Register A 31

§ IMC49

__IO uint8_t IMC49

interrupt Mode Control Register A 49

§ IMC50

__IO uint8_t IMC50

interrupt Mode Control Register A 50

§ IMC51

__IO uint8_t IMC51

interrupt Mode Control Register A 51

§ IMC52

__IO uint8_t IMC52

interrupt Mode Control Register A 52

§ IMC53

__IO uint8_t IMC53

interrupt Mode Control Register A 53

§ IMC54

__IO uint8_t IMC54

interrupt Mode Control Register A 54

§ IMC55

__IO uint8_t IMC55

interrupt Mode Control Register A 55

§ IMC56

__IO uint8_t IMC56

interrupt Mode Control Register A 56

§ IMC57

__IO uint8_t IMC57

interrupt Mode Control Register A 57

§ NIC00

__IO uint8_t NIC00

Non Maskable interrupt Mode Control Register A 00

§ RESERVED0

uint8_t RESERVED0

§ RESERVED1

uint8_t RESERVED1

§ RESERVED2

uint8_t RESERVED2

§ RESERVED3

uint8_t RESERVED3

The documentation for this struct was generated from the following files: