TMPM4G9  V1.0.0.0

16-bit Timer/Event Counter (TB) More...

#include <TMPM4G6.h>

Data Fields

__IO uint32_t MOD
 
uint32_t RESERVED0 [15]
 
__IO uint32_t RUNA
 
__IO uint32_t CRA
 
__IO uint32_t CAPCRA
 
__O uint32_t OUTCRA0
 
__IO uint32_t OUTCRA1
 
__IO uint32_t STA
 
__IO uint32_t IMA
 
__I uint32_t TMRA
 
__IO uint32_t RELDA
 
__IO uint32_t RGA0
 
__IO uint32_t RGA1
 
__I uint32_t CAPA0
 
__I uint32_t CAPA1
 
__IO uint32_t DMAA
 
uint32_t RESERVED1 [2]
 
__IO uint32_t RUNB
 
__IO uint32_t CRB
 
__IO uint32_t CAPCRB
 
__O uint32_t OUTCRB0
 
__IO uint32_t OUTCRB1
 
__IO uint32_t STB
 
__IO uint32_t IMB
 
__I uint32_t TMRB
 
__IO uint32_t RELDB
 
__IO uint32_t RGB0
 
__IO uint32_t RGB1
 
__I uint32_t CAPB0
 
__I uint32_t CAPB1
 
__IO uint32_t DMAB
 
uint32_t RESERVED2 [2]
 
__IO uint32_t RUNC
 
__IO uint32_t CRC
 
__IO uint32_t CAPCRC
 
__O uint32_t OUTCRC0
 
__IO uint32_t OUTCRC1
 
__IO uint32_t STC
 
__IO uint32_t IMC
 
__I uint32_t TMRC
 
__IO uint32_t RELDC
 
__IO uint32_t RGC0
 
__IO uint32_t RGC1
 
__I uint32_t CAPC0
 
__I uint32_t CAPC1
 
__IO uint32_t DMAC
 
__IO uint32_t PLSCR
 

Detailed Description

16-bit Timer/Event Counter (TB)

Field Documentation

§ CAPA0

__I uint32_t CAPA0

T32A Timer Capture A0 Register

§ CAPA1

__I uint32_t CAPA1

T32A Timer Cupture A1 Register

§ CAPB0

__I uint32_t CAPB0

T32A Timer Capture B0 Register

§ CAPB1

__I uint32_t CAPB1

T32A Timer Capture B1 Register

§ CAPC0

__I uint32_t CAPC0

T32A Timer Capture C0 Register

§ CAPC1

__I uint32_t CAPC1

T32A Capture Register C1

§ CAPCRA

__IO uint32_t CAPCRA

T32A Capture Control Register A

§ CAPCRB

__IO uint32_t CAPCRB

T32A Capture Control Register B

§ CAPCRC

__IO uint32_t CAPCRC

T32A Capture Control Register C

§ CRA

__IO uint32_t CRA

T32A Counter Control Register A

§ CRB

__IO uint32_t CRB

T32A Counter Control Register B

§ CRC

__IO uint32_t CRC

T32A Counter Control Register C

§ DMAA

__IO uint32_t DMAA

T32A DMA Request Enable Register A

§ DMAB

__IO uint32_t DMAB

T32A DMA Request Enable Register B

§ DMAC

__IO uint32_t DMAC

T32A DMA Request Enable Register C

§ IMA

__IO uint32_t IMA

T32A Interrupt Mask Register A

§ IMB

__IO uint32_t IMB

T32A Interrupt Mask Register B

§ IMC

__IO uint32_t IMC

T32A Interrupt Mask Register C

§ MOD

__IO uint32_t MOD

T32A Mode Register

§ OUTCRA0

__O uint32_t OUTCRA0

T32A Output Control Register A0

§ OUTCRA1

__IO uint32_t OUTCRA1

T32A Output Control Register A1

§ OUTCRB0

__O uint32_t OUTCRB0

T32A Output Control Register B0

§ OUTCRB1

__IO uint32_t OUTCRB1

T32A Output Control Register B1

§ OUTCRC0

__O uint32_t OUTCRC0

T32A Output Control Register C0

§ OUTCRC1

__IO uint32_t OUTCRC1

T32A Output Control Register C1

§ PLSCR

__IO uint32_t PLSCR

T32A Pulse Count Control Register

§ RELDA

__IO uint32_t RELDA

T32A Counter Reload Register A

§ RELDB

__IO uint32_t RELDB

T32A Counter Reload Register B

§ RELDC

__IO uint32_t RELDC

T32A Counter Reload Register C

§ RESERVED0

uint32_t RESERVED0

§ RESERVED1

uint32_t RESERVED1

§ RESERVED2

uint32_t RESERVED2

§ RGA0

__IO uint32_t RGA0

T32A Timer Register A0

§ RGA1

__IO uint32_t RGA1

T32A Timer Register A1

§ RGB0

__IO uint32_t RGB0

T32A Timer Register B0

§ RGB1

__IO uint32_t RGB1

T32A Timer Register B1

§ RGC0

__IO uint32_t RGC0

T32A Timer Register C0

§ RGC1

__IO uint32_t RGC1

T32A Timer Register C1

§ RUNA

__IO uint32_t RUNA

T32A Run Register A

§ RUNB

__IO uint32_t RUNB

T32A Run Register B

§ RUNC

__IO uint32_t RUNC

T32A Run Register C

§ STA

__IO uint32_t STA

T32A Status Register A

§ STB

__IO uint32_t STB

T32A Status Register B

§ STC

__IO uint32_t STC

T32A Status Register C

§ TMRA

__I uint32_t TMRA

T32A Counter Capture Register A

§ TMRB

__I uint32_t TMRB

T32A Counter Capture Register B

§ TMRC

__I uint32_t TMRC

T32A Counter Capture Register C


The documentation for this struct was generated from the following files: