TMPM4G(1) Group Peripheral Driver User Manual
V1.0.0.0
|
Modules | |
Null Pointer | |
Null Pointer. | |
Parameter Check Result | |
Whether the parameter is specified or not. | |
Result | |
TSPI Result Macro Definition. | |
SW Reset | |
Software Rest Macro Definition. | |
TSPI Enable/Disable Control | |
Enable/Disable TSPIE Macro Definition. | |
Trigger Control | |
Enable/Disable TRGEN Macro Definition. | |
Transmission Control | |
Enable/Disable TRXE Macro Definition. | |
Transmission Mode | |
TSPIIMS Mode Macro Definition. | |
Operation Select | |
Master/Slave MSTR Operation Macro Definition. | |
Transfer Mode | |
Transfer Mode TMMD Macro Definition. | |
CSSEL Select | |
TSPIIxCS0/1/2/3 Select Macro Definition. | |
Transfer Frame Range | |
Transfer Frame Range Macro Definition. | |
IDLE Output Value | |
IDLE time Output Value TIDLE Macro Definition. | |
RXDLY Value | |
IDLE time Output Value TIDLE Macro Definition. | |
Underrun Occur Output Value | |
In case of Under Run Output Value TXDEMP Macro Definition. | |
Tx Fill Level | |
Transmit Fill Level Macro Definition. | |
Rx Fill Level | |
Receive Fill Level Macro Definition. | |
Tx FIFO Interrupt | |
Enable/Disable Transmit FIFO Interrupt Macro Definition. | |
Tx Interrupt | |
Enable/Disable Transmit Interrupt Macro Definition. | |
Rx FIFO Interrupt | |
Enable/Disable Receive FIFO Interrupt Macro Definition. | |
Rx Interrupt | |
Enable/Disable Receive Interrupt Macro Definition. | |
Error Interrupt | |
Enable/Disable Error Interrupt Macro Definition. | |
Tx DMA Interrupt | |
Enable/Disable Transmit DMA Interrupt Macro Definition. | |
Rx DMA Interrupt | |
Enable/Disable Receive DMA Interrupt Macro Definition. | |
Tx Buffer Clear | |
Tx Buffer Clear Macro Definition. | |
Rx Buffer Clear | |
Rx Buffer Clear Macro Definition. | |
Baudrate Input Clock | |
Baudrate Input Clock Macro Definition. | |
Baudrate Divider | |
Baudrate IDivider Macro Definition. | |
Data Direction | |
Data Direction Macro Definition. | |
Data Length | |
Data Length Macro Definition. | |
Frame Interval time | |
Frame Interval time Macro Definition. | |
TSPIxCS3 Polarity | |
TSPIxCS3 Polarity Macro Definition. | |
TSPIxCS2 Polarity | |
TSPIxCS2 Polarity Macro Definition. | |
TSPIxCS1 Polarity | |
TSPIxCS1 Polarity Macro Definition. | |
TSPIxCS0 Polarity | |
TSPIxCS0 Polarity Macro Definition. | |
Serial Clock Polarity | |
Serial Clock Polarity Macro Definition. | |
Serial Clock IDLE Polarity | |
Serial Clock IDLE Polarity Macro Definition. | |
Minimum IDLE Time | |
Minimum IDLE Time Macro Definition. | |
Serial Clock Delay | |
Serial Clock Delay Macro Definition. | |
Negate Delay | |
Negate Delay Macro Definition. | |
Parity Enable | |
Enable/Disable Parity Macro Definition. | |
Parity Bit | |
Parity Bit Macro Definition. | |
Status Setting Flag | |
Enable/Disable Status Setting Flag Macro Definition. | |
Transmitting State Flag | |
Transmitting State Flag Macro Definition. | |
Transmitting Complete Flag | |
Transmitting Complete Flag Macro Definition. | |
Transmitting FIFO Interrupt Flag | |
Transmitting FIFO Interrupt Flag Macro Definition. | |
Transmitting FIFO Empty Flag | |
Transmitting FIFO Empty Flag Macro Definition. | |
Current Transmitting FIFO Level | |
Current Transmitting FIFO Level Macro Definition. | |
Receive State Flag | |
Receive State Flag Macro Definition. | |
Receive Complete Flag | |
Receive Complete Flag Macro Definition. | |
Receiving FIFO Interrupt Flag | |
Rx FIFO Interrupt Flag Macro Definition. | |
Receiving FIFO Full Flag | |
Receiving FIFO Full Flag Macro Definition. | |
Current Receive FIFO Level | |
Current Receive FIFO Level Macro Definition. | |
Trigger Error | |
Trigger Error Macro Definition. | |
Underrun Error | |
Underrun Error Macro Definition. | |
Overrun Error | |
Overrun Error Macro Definition. | |
Parity Error | |
Parity Error Macro Definition. | |
Data allign | |
Data allign Macro Definition. | |
FIFO MAX | |
FIFO MAX LEVEL. | |
Error Code | |
Error Code Macro Definition. | |
Receive Buffer size | |
Error Code Macro Definition. | |
Transfer Type | |
DMA transfer type. | |
TSPIxDR_MASK Macro Definition. | |
#define | TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) |
#define | TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) |
#define | TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) |
#define | TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) |
#define | TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) |
#define | TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) |
#define | TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) |
#define | TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) |
#define | TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) |
#define | TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) |
#define | TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) |
#define | TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) |
#define | TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) |
#define | TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) |
#define | TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) |
#define | TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) |
#define | TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) |
#define | TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) |
#define | TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) |
#define | TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) |
#define | TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) |
#define | TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) |
#define | TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) |
#define | TSPI_DR_37BIT_MASK ((uint32_t)0x7FFFFFFF) |
TSPI _DATA_LENGTH Macro Definition. | |
#define | DATA_LENGTH_8 ((uint32_t)0x08) |
#define | DATA_LENGTH_9 ((uint32_t)0x09) |
#define | DATA_LENGTH_10 ((uint32_t)0x0a) |
#define | DATA_LENGTH_11 ((uint32_t)0x0b) |
#define | DATA_LENGTH_12 ((uint32_t)0x0c) |
#define | DATA_LENGTH_13 ((uint32_t)0x0d) |
#define | DATA_LENGTH_14 ((uint32_t)0x0e) |
#define | DATA_LENGTH_15 ((uint32_t)0x0f) |
#define | DATA_LENGTH_16 ((uint32_t)0x10) |
#define | DATA_LENGTH_17 ((uint32_t)0x11) |
#define | DATA_LENGTH_18 ((uint32_t)0x12) |
#define | DATA_LENGTH_19 ((uint32_t)0x13) |
#define | DATA_LENGTH_20 ((uint32_t)0x14) |
#define | DATA_LENGTH_21 ((uint32_t)0x15) |
#define | DATA_LENGTH_22 ((uint32_t)0x16) |
#define | DATA_LENGTH_23 ((uint32_t)0x17) |
#define | DATA_LENGTH_24 ((uint32_t)0x18) |
#define | DATA_LENGTH_25 ((uint32_t)0x19) |
#define | DATA_LENGTH_26 ((uint32_t)0x1a) |
#define | DATA_LENGTH_27 ((uint32_t)0x1b) |
#define | DATA_LENGTH_28 ((uint32_t)0x1c) |
#define | DATA_LENGTH_29 ((uint32_t)0x1d) |
#define | DATA_LENGTH_30 ((uint32_t)0x1e) |
#define | DATA_LENGTH_31 ((uint32_t)0x1f) |
#define | DATA_LENGTH_32 ((uint32_t)0x20) |
#define DATA_LENGTH_10 ((uint32_t)0x0a) |
10 bit
#define DATA_LENGTH_11 ((uint32_t)0x0b) |
11 bit
#define DATA_LENGTH_12 ((uint32_t)0x0c) |
12 bit
#define DATA_LENGTH_13 ((uint32_t)0x0d) |
13 bit
#define DATA_LENGTH_14 ((uint32_t)0x0e) |
14 bit
#define DATA_LENGTH_15 ((uint32_t)0x0f) |
15 bit
#define DATA_LENGTH_16 ((uint32_t)0x10) |
16 bit
#define DATA_LENGTH_17 ((uint32_t)0x11) |
17 bit
#define DATA_LENGTH_18 ((uint32_t)0x12) |
18 bit
#define DATA_LENGTH_19 ((uint32_t)0x13) |
19 bit
#define DATA_LENGTH_20 ((uint32_t)0x14) |
20 bit
#define DATA_LENGTH_21 ((uint32_t)0x15) |
21 bit
#define DATA_LENGTH_22 ((uint32_t)0x16) |
22 bit
#define DATA_LENGTH_23 ((uint32_t)0x17) |
23 bit
#define DATA_LENGTH_24 ((uint32_t)0x18) |
24 bit
#define DATA_LENGTH_25 ((uint32_t)0x19) |
25 bit
#define DATA_LENGTH_26 ((uint32_t)0x1a) |
26 bit
#define DATA_LENGTH_27 ((uint32_t)0x1b) |
27 bit
#define DATA_LENGTH_28 ((uint32_t)0x1c) |
28 bit
#define DATA_LENGTH_29 ((uint32_t)0x1d) |
29 bit
#define DATA_LENGTH_30 ((uint32_t)0x1e) |
30 bit
#define DATA_LENGTH_31 ((uint32_t)0x1f) |
31 bit
#define DATA_LENGTH_32 ((uint32_t)0x20) |
32 bit
#define DATA_LENGTH_8 ((uint32_t)0x08) |
8 bit
#define DATA_LENGTH_9 ((uint32_t)0x09) |
9 bit
#define TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) |
DR :Mask for 8bit
#define TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) |
DR :Mask for 8bit
#define TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) |
DR :Mask for 8bit
#define TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) |
DR :Mask for 8bit
#define TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) |
DR :Mask for 8bit
#define TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) |
DR :Mask for 8bit
#define TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) |
DR :Mask for 8bit
#define TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) |
DR :Mask for 8bit
#define TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) |
DR :Mask for 8bit
#define TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) |
DR :Mask for 8bit
#define TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) |
DR :Mask for 8bit
#define TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) |
DR :Mask for 8bit
#define TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) |
DR :Mask for 8bit
#define TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) |
DR :Mask for 8bit
#define TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) |
DR :Mask for 8bit
#define TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) |
DR :Mask for 8bit
#define TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) |
DR :Mask for 8bit
#define TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) |
DR :Mask for 8bit
#define TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) |
DR :Mask for 8bit
#define TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) |
DR :Mask for 8bit
#define TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) |
DR :Mask for 8bit
#define TSPI_DR_37BIT_MASK ((uint32_t)0x7FFFFFFF) |
DR :Mask for 8bit
#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) |
DR :Mask for 8bit
#define TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) |
DR :Mask for 8bit