TMPM4G9
V1.0.0.0
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#include "TMPM4Gx.h"
Macros | |
#define | SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ |
#define | SIWDEN_Val (0x00000000UL) /* SIWD Disable */ |
#define | SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ |
#define | CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ |
#define | SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */ |
#define | SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */ |
#define | STBYCR_Val (0x00000000UL) |
#define | CG_8M_MUL_20_FPLL (0x00245028UL<<8U) /* fPLL = 8MHz * 20 */ |
#define | CG_10M_MUL_16_FPLL (0x002E5020UL<<8U) /* fPLL = 10MHz * 16 */ |
#define | CG_12M_MUL_13_3125_FPLL (0x0036DA1AUL<<8U) /* fPLL = 12MHz * 13.3125 */ |
#define | CG_16M_MUL_10_FPLL (0x0048D014UL<<8U) /* fPLL = 16MHz * 10 */ |
#define | CG_20M_MUL_8_FPLL (0x005AD010UL<<8U) /* fPLL = 20MHz * 8 */ |
#define | CG_PLL0SEL_PLL0ON_SET (0x00000001UL) |
#define | CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL) |
#define | CG_PLL0SEL_PLL0SEL_SET (0x00000002UL) |
#define | CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL) |
#define | CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U) |
#define | CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U) |
#define | CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U) |
#define | CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL) |
#define | CG_OSCCR_EOSCEN_SET (0x00000002UL) |
#define | CG_OSCCR_OSCSEL_SET (0x00000100UL) |
#define | CG_WUPHCR_WUON_START_SET (0x00000001UL) |
#define | EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */ |
#define | CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */ |
#define | PLL0SEL_Ready CG_20M_MUL_8_FPLL |
#define | PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) |
#define | PLL0SEL_MASK (0xFFFFFF00UL) |
#define | EOSC_8M (8000000UL) |
#define | EOSC_10M (10000000UL) |
#define | EOSC_12M (12000000UL) |
#define | EOSC_16M (16000000UL) |
#define | EOSC_20M (20000000UL) |
#define | IOSC_10M (10000000UL) |
#define | EXTALH EOSC_20M /* External high-speed oscillator freq */ |
#define | IXTALH IOSC_10M /* Internal high-speed oscillator freq */ |
#define | EOSC_8M_DIV2_PLLON (160000000UL) /* 8.00MHz * 40.0000 / 2 */ |
#define | EOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ |
#define | EOSC_12M_DIV2_PLLON (159750000UL) /* 12.00MHz * 26.6250 / 2 */ |
#define | EOSC_16M_DIV2_PLLON (160000000UL) /* 16.00MHz * 20.0000 / 2 */ |
#define | EOSC_20M_DIV2_PLLON (160000000UL) /* 20.00MHz * 16.0000 / 2 */ |
#define | IOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ |
#define | HZ_1M (1000000UL) |
#define | WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ |
#define | INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ |
#define | LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ |
#define | WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR<WUPT11:0> = (warm-up time(us) * IXTALH - 16) / 16 */ |
#define | WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) |
#define | WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) |
#define | CORE_TALH (EXTALH) |
#define | __CORE_CLK EOSC_20M_DIV2_PLLON /* output clock is 160MHz */ |
#define | __CORE_SYS (__CORE_CLK) |
Functions | |
void | SystemCoreClockUpdate (void) |
Update SystemCoreClock according register values. More... | |
void | SystemInit (void) |
Setup the microcontroller system. Initialize the System. More... | |
Variables | |
uint32_t | SystemCoreClock = __CORE_SYS |
uint32_t | CoreClockInput = 0U |
#define __CORE_CLK EOSC_20M_DIV2_PLLON /* output clock is 160MHz */ |
#define __CORE_SYS (__CORE_CLK) |
#define CG_10M_MUL_16_FPLL (0x002E5020UL<<8U) /* fPLL = 10MHz * 16 */ |
#define CG_12M_MUL_13_3125_FPLL (0x0036DA1AUL<<8U) /* fPLL = 12MHz * 13.3125 */ |
#define CG_16M_MUL_10_FPLL (0x0048D014UL<<8U) /* fPLL = 16MHz * 10 */ |
#define CG_20M_MUL_8_FPLL (0x005AD010UL<<8U) /* fPLL = 20MHz * 8 */ |
#define CG_8M_MUL_20_FPLL (0x00245028UL<<8U) /* fPLL = 8MHz * 20 */ |
#define CG_OSCCR_EOSCEN_SET (0x00000002UL) |
#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL) |
#define CG_OSCCR_OSCSEL_SET (0x00000100UL) |
#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL) |
#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL) |
#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL) |
#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL) |
#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U) |
#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U) |
#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U) |
#define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */ |
#define CG_WUPHCR_WUON_START_SET (0x00000001UL) |
#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ |
#define CORE_TALH (EXTALH) |
#define EOSC_10M (10000000UL) |
#define EOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ |
#define EOSC_12M (12000000UL) |
#define EOSC_12M_DIV2_PLLON (159750000UL) /* 12.00MHz * 26.6250 / 2 */ |
#define EOSC_16M (16000000UL) |
#define EOSC_16M_DIV2_PLLON (160000000UL) /* 16.00MHz * 20.0000 / 2 */ |
#define EOSC_20M (20000000UL) |
#define EOSC_20M_DIV2_PLLON (160000000UL) /* 20.00MHz * 16.0000 / 2 */ |
#define EOSC_8M (8000000UL) |
#define EOSC_8M_DIV2_PLLON (160000000UL) /* 8.00MHz * 40.0000 / 2 */ |
#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */ |
#define EXTALH EOSC_20M /* External high-speed oscillator freq */ |
#define HZ_1M (1000000UL) |
#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ |
#define IOSC_10M (10000000UL) |
#define IOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ |
#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ |
#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ |
#define PLL0SEL_MASK (0xFFFFFF00UL) |
#define PLL0SEL_Ready CG_20M_MUL_8_FPLL |
#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) |
#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ |
#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ |
#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ |
#define STBYCR_Val (0x00000000UL) |
#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */ |
#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */ |
#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ |
#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) |
#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) |
#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR<WUPT11:0> = (warm-up time(us) * IXTALH - 16) / 16 */ |
void SystemCoreClockUpdate | ( | void | ) |
Update SystemCoreClock according register values.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
Initialize the system
none |
void SystemInit | ( | void | ) |
Setup the microcontroller system. Initialize the System.
Setup the microcontroller system. Initialize the System and update the SystemCoreClock variable.
Initialize the system
none |
uint32_t CoreClockInput = 0U |
High speed Clock Frequency
uint32_t SystemCoreClock = __CORE_SYS |
System Clock Frequency (Core Clock)