TMPM4G9  V1.0.0.0

DMA Controller. More...

#include <TMPM4G6.h>

Data Fields

__I uint32_t INTSTATUS
 
__I uint32_t INTTCSTATUS
 
__O uint32_t INTTCCLEAR
 
__I uint32_t INTERRORSTATUS
 
__O uint32_t INTERRCLR
 
__I uint32_t RAWINTTCSTATUS
 
__I uint32_t RAWINTERRORSTATUS
 
__I uint32_t ENBLDCHNS
 
__IO uint32_t SOFTBREQ
 
__IO uint32_t SOFTSREQ
 
uint32_t RESERVED0 [2]
 
__IO uint32_t CONFIGURATION
 
uint32_t RESERVED1 [51]
 
__IO uint32_t C0SRCADDR
 
__IO uint32_t C0DESTADDR
 
__IO uint32_t C0LLI
 
__IO uint32_t C0CONTROL
 
__IO uint32_t C0CONFIGURATION
 
uint32_t RESERVED2 [3]
 
__IO uint32_t C1SRCADDR
 
__IO uint32_t C1DESTADDR
 
__IO uint32_t C1LLI
 
__IO uint32_t C1CONTROL
 
__IO uint32_t C1CONFIGURATION
 

Detailed Description

DMA Controller.

Device Specific Peripheral registers structures

Field Documentation

§ C0CONFIGURATION

__IO uint32_t C0CONFIGURATION

DMAC Channel 0 Configuration Register

§ C0CONTROL

__IO uint32_t C0CONTROL

DMAC Channel 0 Control Register

§ C0DESTADDR

__IO uint32_t C0DESTADDR

DMAC Channel 0 Destination Address Register

§ C0LLI

__IO uint32_t C0LLI

DMAC Channel 0 Linked List Item Register

§ C0SRCADDR

__IO uint32_t C0SRCADDR

DMAC Channel 0 Source Address Register

§ C1CONFIGURATION

__IO uint32_t C1CONFIGURATION

DMAC Channel 1 Configuration Register

§ C1CONTROL

__IO uint32_t C1CONTROL

DMAC Channel 1 Control Register

§ C1DESTADDR

__IO uint32_t C1DESTADDR

DMAC Channel 1 Destination Address Register

§ C1LLI

__IO uint32_t C1LLI

DMAC Channel 1 Linked List Item Register

§ C1SRCADDR

__IO uint32_t C1SRCADDR

DMAC Channel 1 Source Address Register

§ CONFIGURATION

__IO uint32_t CONFIGURATION

DMAC Configuration Register

§ ENBLDCHNS

__I uint32_t ENBLDCHNS

DMAC Enabled Channel Register

§ INTERRCLR

__O uint32_t INTERRCLR

DMAC Interrupt Error Clear Register

§ INTERRORSTATUS

__I uint32_t INTERRORSTATUS

DMAC Interrupt Error Status Register

§ INTSTATUS

__I uint32_t INTSTATUS

DMAC Interrupt Status Register

§ INTTCCLEAR

__O uint32_t INTTCCLEAR

DMAC Interrupt Terminal Count Clear Register

§ INTTCSTATUS

__I uint32_t INTTCSTATUS

DMAC Interrupt Terminal Count Status Register

§ RAWINTERRORSTATUS

__I uint32_t RAWINTERRORSTATUS

DMAC Raw Error Interrupt Status Register

§ RAWINTTCSTATUS

__I uint32_t RAWINTTCSTATUS

DMAC Raw Interrupt Terminal Count Status Register

§ RESERVED0

uint32_t RESERVED0

§ RESERVED1

uint32_t RESERVED1

§ RESERVED2

uint32_t RESERVED2

§ SOFTBREQ

__IO uint32_t SOFTBREQ

DMAC Software Burst Request Register

§ SOFTSREQ

__IO uint32_t SOFTSREQ

DMAC Software Single Request Register


The documentation for this struct was generated from the following files: