TMPM4G(1) Group Peripheral Driver User Manual
V1.0.0.0
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This file provides all the functions prototypes for T32A driver. More...
#include "txz_driver_def.h"
Go to the source code of this file.
Data Structures | |
struct | t32a_mode_t |
TimerA Mode Setting structure definition. More... | |
struct | t32a_runx_t |
TimerA Run Control Setting structure definition. More... | |
struct | t32a_crx_t |
Counter Register Control Setting structure definition. More... | |
struct | t32a_outcrx0_t |
TimerA Output Control Setting structure definition. More... | |
struct | t32a_outcrx1_t |
T32AxOUTA Control Setting structure definition. More... | |
struct | t32a_capcrx_t |
Capture Control Setting structure definition. More... | |
struct | t32a_rgx0_t |
T32A Timer Register x0 Setting structure definition. More... | |
struct | t32a_rgx1_t |
T32A Timer Register x1 Setting structure definition. More... | |
struct | t32a_tmrx_t |
T32A Counter Capture Register A Setting structure definition. More... | |
struct | t32a_reldx_t |
T32A Counter Reload Register Setting structure definition. More... | |
struct | t32a_capx0_t |
T32A Capture Register x0 Setting structure definition. More... | |
struct | t32a_capx1_t |
T32A Capture Register x0 Setting structure definition. More... | |
struct | t32a_imx_t |
Interrupt mask register Setting structure definition. More... | |
struct | t32a_stx_t |
Status register structure definition. More... | |
struct | t32a_dma_req_t |
DMA Request register setting structure definition. More... | |
struct | t32a_pulse_cr_t |
Pulse Count Control register setting structure definition. More... | |
struct | t32a_initial_setting_t |
Initial Timer setting structure definition. More... | |
struct | t32a_initial_mode_t |
Initial Mode setting structure definition. More... | |
struct | t32a_handle |
T32A handle structure definition. More... | |
Macros | |
#define | T32A_RESULT_SUCCESS (0) |
#define | T32A_RESULT_FAILURE (-1) |
#define | T32A_READ_FAILURE (0xFFFFFFFF) |
#define | T32A_NULL ((void *)0) |
#define | T32A_DBG_HALT_RUN ((uint32_t)0x00000000) |
#define | T32A_DBG_HALT_STOP ((uint32_t)0x00000002) |
#define | T32A_MODE_16 ((uint32_t)0x00000000) |
#define | T32A_MODE_32 ((uint32_t)0x00000001) |
#define | T32A_RUNFLG_RUN ((uint32_t)0x00000010) |
#define | T32A_RUNFLG_STOP ((uint32_t)0x00000000) |
#define | T32A_COUNT_DONT_STOP ((uint32_t)0x0000000) |
#define | T32A_COUNT_STOP ((uint32_t)0x0000004) |
#define | T32A_COUNT_DONT_START ((uint32_t)0x0000000) |
#define | T32A_COUNT_START ((uint32_t)0x0000002) |
#define | T32A_RUN_DISABLE ((uint32_t)0x00000000) |
#define | T32A_RUN_ENABLE ((uint32_t)0x00000001) |
#define | T32A_PRSCLx_1 ((uint32_t)0x00000000) |
#define | T32A_PRSCLx_2 ((uint32_t)0x10000000) |
#define | T32A_PRSCLx_8 ((uint32_t)0x20000000) |
#define | T32A_PRSCLx_32 ((uint32_t)0x30000000) |
#define | T32A_PRSCLx_128 ((uint32_t)0x40000000) |
#define | T32A_PRSCLx_256 ((uint32_t)0x50000000) |
#define | T32A_PRSCLx_512 ((uint32_t)0x60000000) |
#define | T32A_PRSCLx_1024 ((uint32_t)0x70000000) |
#define | T32A_CLKx_PRSCLx ((uint32_t)0x00000000) |
#define | T32A_CLKx_INTRG ((uint32_t)0x01000000) |
#define | T32A_CLKx_TIM_RISING_EDGE ((uint32_t)0x02000000) |
#define | T32A_CLKx_TIM_TRAILING_EDGE ((uint32_t)0x03000000) |
#define | T32A_CLKx_EXTTRG_RISING_EDGE ((uint32_t)0x04000000) |
#define | T32A_CLKx_EXTTRG_TRAILING_EDGE ((uint32_t)0x05000000) |
#define | T32A_WBF_DISABLE ((uint32_t)0x00000000) |
#define | T32A_WBF_ENABLE ((uint32_t)0x00100000) |
#define | T32A_COUNT_UP ((uint32_t)0x00000000) |
#define | T32A_COUNT_DOWN ((uint32_t)0x00010000) |
#define | T32A_COUNT_UPDOWN ((uint32_t)0x00020000) |
#define | T32A_COUNT_PLS ((uint32_t)0x00030000) |
#define | T32A_RELOAD_NON ((uint32_t)0x00000000) |
#define | T32A_RELOAD_INTRG ((uint32_t)0x00000100) |
#define | T32A_RELOAD_EXTTRG_RISING_EDGE ((uint32_t)0x00000200) |
#define | T32A_RELOAD_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000300) |
#define | T32A_RELOAD_TIM_RISING_EDGE ((uint32_t)0x00000400) |
#define | T32A_RELOAD_TIM_TRAILING_EDGE ((uint32_t)0x00000500) |
#define | T32A_RELOAD_SYNC ((uint32_t)0x00000600) |
#define | T32A_RELOAD_TREGx ((uint32_t)0x00000700) |
#define | T32A_STOP_NON ((uint32_t)0x00000000) |
#define | T32A_STOP_INTRG ((uint32_t)0x00000010) |
#define | T32A_STOP_EXTTRG_RISING_EDGE ((uint32_t)0x00000020) |
#define | T32A_STOP_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000030) |
#define | T32A_STOP_TIM_RISING_EDGE ((uint32_t)0x00000040) |
#define | T32A_STOP_TIM_TRAILING_EDGE ((uint32_t)0x00000050) |
#define | T32A_STOP_SYNC ((uint32_t)0x00000060) |
#define | T32A_STOP_TREGx ((uint32_t)0x00000070) |
#define | T32A_START_NON ((uint32_t)0x00000000) |
#define | T32A_START_INTRG ((uint32_t)0x00000001) |
#define | T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) |
#define | T32A_START_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000003) |
#define | T32A_START_TIM_RISING_EDGE ((uint32_t)0x00000004) |
#define | T32A_START_TIM_TRAILING_EDGE ((uint32_t)0x00000005) |
#define | T32A_START_SYNC ((uint32_t)0x00000006) |
#define | T32A_START_Rsvd ((uint32_t)0x00000007) |
#define | T32A_OCR_DISABLE ((uint32_t)0x00000000) |
#define | T32A_OCR_SET ((uint32_t)0x00000001) |
#define | T32A_OCR_CLR ((uint32_t)0x00000002) |
#define | T32A_OCR_INVERSION ((uint32_t)0x00000003) |
#define | T32A_OCRCAPx1_DISABLE ((uint32_t)0x00000000) |
#define | T32A_OCRCAPx1_SET ((uint32_t)0x00000040) |
#define | T32A_OCRCAPx1_CLR ((uint32_t)0x00000080) |
#define | T32A_OCRCAPx1_INVERSION ((uint32_t)0x000000C0) |
#define | T32A_OCRCAPx0_DISABLE ((uint32_t)0x00000000) |
#define | T32A_OCRCAPx0_SET ((uint32_t)0x00000010) |
#define | T32A_OCRCAPx0_CLR ((uint32_t)0x00000020) |
#define | T32A_OCRCAPx0_INVERSION ((uint32_t)0x00000030) |
#define | T32A_OCRCMPx1_DISABLE ((uint32_t)0x00000000) |
#define | T32A_OCRCMPx1_SET ((uint32_t)0x00000004) |
#define | T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) |
#define | T32A_OCRCMPx1_INVERSION ((uint32_t)0x0000000C) |
#define | T32A_OCRCMPx0_DISABLE ((uint32_t)0x00000000) |
#define | T32A_OCRCMPx0_SET ((uint32_t)0x00000001) |
#define | T32A_OCRCMPx0_CLR ((uint32_t)0x00000002) |
#define | T32A_OCRCMPx0_INVERSION ((uint32_t)0x00000003) |
#define | T32A_RGx0_MASK ((uint32_t)0x0000FFFF) |
#define | T32A_RGC0_MASK ((uint32_t)0xFFFFFFFF) |
#define | T32A_RGx1_MASK ((uint32_t)0x0000FFFF) |
#define | T32A_RGC1_MASK ((uint32_t)0xFFFFFFFF) |
#define | T32A_TMRx_MASK ((uint32_t)0x0000FFFF) |
#define | T32A_TMRC_MASK ((uint32_t)0xFFFFFFFF) |
#define | T32A_RELDx_MASK ((uint32_t)0x0000FFFF) |
#define | T32A_RELDC_MASK ((uint32_t)0xFFFFFFFF) |
#define | T32A_CAPMx1_DISABLE ((uint32_t)0x00000000) |
#define | T32A_CAPMx1_INTRG ((uint32_t)0x00000010) |
#define | T32A_CAPMx1_INx0_RISING_EDGE ((uint32_t)0x00000020) |
#define | T32A_CAPMx1_INx0_TRAILING_EDGE ((uint32_t)0x00000030) |
#define | T32A_CAPMx1_INx1_RISING_EDGE ((uint32_t)0x00000040) |
#define | T32A_CAPMx1_INx1_TRAILING_EDGE ((uint32_t)0x00000050) |
#define | T32A_CAPMx1_TIM_RISING_EDGE ((uint32_t)0x00000060) |
#define | T32A_CAPMx1_TIM_TRAILING_EDGE ((uint32_t)0x00000070) |
#define | T32A_CAPMx0_DISABLE ((uint32_t)0x00000000) |
#define | T32A_CAPMx0_INTRG ((uint32_t)0x00000001) |
#define | T32A_CAPMx0_INx0_RISING_EDGE ((uint32_t)0x00000002) |
#define | T32A_CAPMx0_INx0_TRAILING_EDGE ((uint32_t)0x00000003) |
#define | T32A_CAPMx0_INx1_RISING_EDGE ((uint32_t)0x00000004) |
#define | T32A_CAPMx0_INx1_TRAILING_EDGE ((uint32_t)0x00000005) |
#define | T32A_CAPMx0_TIM_RISING_EDGE ((uint32_t)0x00000006) |
#define | T32A_CAPMx0_TIM_TRAILING_EDGE ((uint32_t)0x00000007) |
#define | T32A_CAPx0_MASK ((uint32_t)0x0000FFFF) |
#define | T32A_CAPC0_MASK ((uint32_t)0xFFFFFFFF) |
#define | T32A_CAPx1_MASK ((uint32_t)0x0000FFFF) |
#define | T32A_CAPC1_MASK ((uint32_t)0xFFFFFFFF) |
#define | T32A_IMSTERR_MASK_NOREQ ((uint32_t)0x00000000) |
#define | T32A_IMSTERR_MASK_REQ ((uint32_t)0x00000010) |
#define | T32A_IMUFx_MASK_NOREQ ((uint32_t)0x00000000) |
#define | T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) |
#define | T32A_IMOFx_MASK_NOREQ ((uint32_t)0x00000000) |
#define | T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) |
#define | T32A_IMx1_MASK_NOREQ ((uint32_t)0x00000000) |
#define | T32A_IMx1_MASK_REQ ((uint32_t)0x00000002) |
#define | T32A_IMx0_MASK_NOREQ ((uint32_t)0x00000000) |
#define | T32A_IMx0_MASK_REQ ((uint32_t)0x00000001) |
#define | T32A_INTSTERR_FLG_MASK ((uint32_t)0x00000010) |
#define | T32A_INTSTERR_FLG_CLR ((uint32_t)0x00000010) |
#define | T32A_INTUFx_FLG_MASK ((uint32_t)0x00000008) |
#define | T32A_INTUFx_FLG_CLR ((uint32_t)0x00000008) |
#define | T32A_INTOFx_FLG_MASK ((uint32_t)0x00000004) |
#define | T32A_INTOFx_FLG_CLR ((uint32_t)0x00000004) |
#define | T32A_INTx1_FLG_MASK ((uint32_t)0x00000002) |
#define | T32A_INTx1_FLG_CLR ((uint32_t)0x00000002) |
#define | T32A_INTx0_FLG_MASK ((uint32_t)0x00000001) |
#define | T32A_INTx0_FLG_CLR ((uint32_t)0x00000001) |
#define | T32A_DMAENx2_DISABLE ((uint32_t)0x00000000) |
#define | T32A_DMAENx2_ENABLE ((uint32_t)0x00000004) |
#define | T32A_DMAENx1_DISABLE ((uint32_t)0x00000000) |
#define | T32A_DMAENx1_ENABLE ((uint32_t)0x00000002) |
#define | T32A_DMAENx0_DISABLE ((uint32_t)0x00000000) |
#define | T32A_DMAENx0_ENABLE ((uint32_t)0x00000001) |
#define | T32A_PDN_NON0 ((uint32_t)0x00000000) |
#define | T32A_PDN_NON1 ((uint32_t)0x00001000) |
#define | T32A_PDN_INC0_RISING_EDGE ((uint32_t)0x00002000) |
#define | T32A_PDN_INC0_TRAILING_EDGE ((uint32_t)0x00003000) |
#define | T32A_PDN_INC1_RISING_EDGE ((uint32_t)0x00004000) |
#define | T32A_PDN_INC1_TRAILING_EDGE ((uint32_t)0x00005000) |
#define | T32A_PDN_INC0_BOTH_EDGE ((uint32_t)0x00006000) |
#define | T32A_PDN_INC1_BOTH_EDGE ((uint32_t)0x00007000) |
#define | T32A_PUP_NON0 ((uint32_t)0x00000000) |
#define | T32A_PUP_NON1 ((uint32_t)0x00000100) |
#define | T32A_PUP_INC0_RISING_EDGE ((uint32_t)0x00000200) |
#define | T32A_PUP_INC0_TRAILING_EDGE ((uint32_t)0x00000300) |
#define | T32A_PUP_INC1_RISING_EDGE ((uint32_t)0x00000400) |
#define | T32A_PUP_INC1_TRAILING_EDGE ((uint32_t)0x00000500) |
#define | T32A_PUP_INC0_BOTH_EDGE ((uint32_t)0x00000600) |
#define | T32A_PUP_INC1_BOTH_EDGE ((uint32_t)0x00000700) |
#define | T32A_NF_NON ((uint32_t)0x00000000) |
#define | T32A_NF_2 ((uint32_t)0x00000010) |
#define | T32A_NF_4 ((uint32_t)0x00000020) |
#define | T32A_NF_8 ((uint32_t)0x00000030) |
#define | T32A_PDIR_FORWARD ((uint32_t)0x00000000) |
#define | T32A_PDIR_BACKWARD ((uint32_t)0x00000002) |
#define | T32A_PMODE_PHASE_2 ((uint32_t)0x00000000) |
#define | T32A_PMODE_PHASE_1 ((uint32_t)0x00000001) |
Typedefs | |
typedef struct t32a_handle | t32a_t |
T32A handle structure definition. More... | |
Enumerations | |
enum | t32_type_t { T32A_TIMERA = 0, T32A_TIMERB, T32A_TIMERC, T32A_TIMERMAX } |
Use of Timer register. More... | |
enum | t32_regnum_t { T32A_REG0 = 0, T32A_REG1, T32A_RELOAD } |
Use of Timer register number. More... | |
enum | t32_mode_t { T32A_MATCH = 0, T32A_OVERFLOW, T32A_UNDERFLOW, T32A_CAPTURE0, T32A_CAPTURE1 } |
Use of Timer register. More... | |
enum | t32_triger_t { T32A_INTRG = 0, T32A_TIM_RISING_EDGE, T32A_TIM_TRAILING_EDGE, T32A_EXTTRG_RISING_EDGE, T32A_EXTTRG_TRAILING_EDGE } |
Use of Timer register. More... | |
Functions | |
TXZ_Result | t32a_mode_init (t32a_t *p_obj) |
TXZ_Result | t32a_timer_init (t32a_t *p_obj, uint32_t type) |
TXZ_Result | t32a_deinit (t32a_t *p_obj, uint32_t type) |
TXZ_Result | t32a_timer_stopIT (t32a_t *p_obj, uint32_t type) |
TXZ_Result | t32a_timer_startIT (t32a_t *p_obj, uint32_t type) |
TXZ_Result | t32a_SWcounter_start (t32a_t *p_obj, uint32_t type) |
TXZ_Result | t32a_SWcounter_stop (t32a_t *p_obj, uint32_t type) |
TXZ_Result | t32a_reg_set (t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value) |
TXZ_Result | t32a_tmr_read (t32a_t *p_obj, uint32_t type, uint32_t *p_val) |
TXZ_Result | t32a_get_status (t32a_t *p_obj, uint32_t *p_status, uint32_t type) |
void | t32a_timer_IRQHandler (t32a_t *p_obj) |
void | t32a_timer_cap0_IRQHandler (t32a_t *p_obj) |
void | t32a_timer_cap1_IRQHandler (t32a_t *p_obj) |
TXZ_Result | t32a_Calculator (uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl) |
This file provides all the functions prototypes for T32A driver.
DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
Copyright(C) Toshiba Electronic Device Solutions Corporation 2019