TMPM4G(1) Group Peripheral Driver User Manual
V1.0.0.0
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This file provides all the functions prototypes for TSPI driver. More...
#include "txz_driver_def.h"
Go to the source code of this file.
Data Structures | |
struct | tspi_receive8_t |
Receive event information structure definition. More... | |
struct | tspi_receive16_t |
Receive event information structure definition. More... | |
struct | tspi_receive32_t |
Receive event information structure definition. More... | |
struct | tspi_receive_t |
Receive event information structure definition. More... | |
struct | tspi_transmit8_t |
Transmit data information structure definition. More... | |
struct | tspi_transmit16_t |
Transmit data information structure definition. More... | |
struct | tspi_transmit32_t |
Transmit data information structure definition. More... | |
struct | tspi_transmit_t |
Transmit data information structure definition. More... | |
struct | tspi_control1_t |
Control Setting structure definition. More... | |
struct | tspi_control2_t |
Control Setting structure definition. More... | |
struct | tspi_control3_t |
Control Setting structure definition. More... | |
struct | tspi_baudrate_t |
Clock setting structure definition. More... | |
struct | tspi_fmtr0_t |
Format control0. More... | |
struct | tspi_fmtr1_t |
Format control1. More... | |
struct | tspi_status_t |
Status register. More... | |
struct | tspi_error_t |
Error flag. More... | |
struct | tspi_initial_setting_t |
Initial setting structure definition. More... | |
struct | tspi_handle |
TSPI handle structure definition. More... | |
Macros | |
#define | TSPI_NULL ((void *)0) |
#define | TSPI_PARAM_OK ((int32_t)1) |
#define | TSPI_PARAM_NG ((int32_t)0) |
#define | TSPI_RESULT_SUCCESS (0) |
#define | TSPI_RESULT_FAILURE (-1) |
#define | TSPI_RESET10 ((uint32_t)0x00000080) |
#define | TSPI_RESET01 ((uint32_t)0x00000040) |
#define | TSPI_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_ENABLE ((uint32_t)0x00000001) |
#define | TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) |
#define | TSPI_TRXE_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_TRXE_ENABLE ((uint32_t)0x00004000) |
#define | TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) |
#define | TSPI_SPI_MODE ((uint32_t)0x00000000) |
#define | TSPI_SIO_MODE ((uint32_t)0x00002000) |
#define | TSPI_MASTER_OPERATION ((uint32_t)0x00001000) |
#define | TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) |
#define | TSPI_TX_ONLY ((uint32_t)0x00000400) |
#define | TSPI_RX_ONLY ((uint32_t)0x00000800) |
#define | TSPI_TWO_WAY ((uint32_t)0x00000C00) |
#define | TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) |
#define | TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) |
#define | TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) |
#define | TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) |
#define | TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) |
#define | TSPI_TRANS_RANGE_CONTINUE ((uint32_t)0x00000000) |
#define | TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000001) |
#define | TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) |
#define | TSPI_TIDLE_Hiz ((uint32_t)0x00000000) |
#define | TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) |
#define | TSPI_TIDLE_LOW ((uint32_t)0x00800000) |
#define | TSPI_TIDLE_HI ((uint32_t)0x00C00000) |
#define | TSPI_RXDLY_SET ((uint32_t)0x00010000) |
#define | TSPI_TXDEMP_LOW ((uint32_t)0x00000000) |
#define | TSPI_TXDEMP_HI ((uint32_t)0x00200000) |
#define | TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) |
#define | TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) |
#define | TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) |
#define | TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) |
#define | TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) |
#define | TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) |
#define | TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) |
#define | TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) |
#define | TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) |
#define | TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) |
#define | TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) |
#define | TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) |
#define | TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) |
#define | TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) |
#define | TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) |
#define | TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) |
#define | TSPI_RX_FILL_LEVEL_8 ((uint32_t)0x00000800) |
#define | TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000F00) |
#define | TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) |
#define | TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) |
#define | TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) |
#define | TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) |
#define | TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) |
#define | TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) |
#define | TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) |
#define | TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) |
#define | TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) |
#define | TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) |
#define | TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) |
#define | TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) |
#define | TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) |
#define | TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) |
#define | TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) |
#define | TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) |
#define | TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) |
#define | TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) |
#define | TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) |
#define | TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) |
#define | TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) |
#define | TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) |
#define | TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) |
#define | TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) |
#define | TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) |
#define | TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) |
#define | TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) |
#define | TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) |
#define | TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) |
#define | TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) |
#define | TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) |
#define | TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) |
#define | TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) |
#define | TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) |
#define | TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) |
#define | TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) |
#define | TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) |
#define | TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) |
#define | TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) |
#define | TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) |
#define | TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) |
#define | TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) |
#define | TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) |
#define | TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) |
#define | TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) |
#define | TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) |
#define | TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) |
#define | TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) |
#define | TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) |
#define | TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) |
#define | TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) |
#define | TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) |
#define | TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) |
#define | TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) |
#define | TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) |
#define | TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) |
#define | TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) |
#define | TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) |
#define | TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) |
#define | TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) |
#define | TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) |
#define | TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) |
#define | TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) |
#define | TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) |
#define | TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) |
#define | TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) |
#define | TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) |
#define | TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) |
#define | TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) |
#define | TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) |
#define | TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) |
#define | TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) |
#define | TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) |
#define | TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) |
#define | TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) |
#define | TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) |
#define | TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) |
#define | TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) |
#define | TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) |
#define | TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) |
#define | TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) |
#define | TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) |
#define | TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) |
#define | TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) |
#define | TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) |
#define | TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) |
#define | TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) |
#define | TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) |
#define | TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) |
#define | TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) |
#define | TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) |
#define | TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) |
#define | TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) |
#define | TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) |
#define | TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) |
#define | TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) |
#define | TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) |
#define | TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) |
#define | TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) |
#define | TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) |
#define | TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) |
#define | TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) |
#define | TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) |
#define | TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) |
#define | TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) |
#define | TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) |
#define | TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) |
#define | TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) |
#define | TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) |
#define | TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) |
#define | TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) |
#define | TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) |
#define | TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) |
#define | TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) |
#define | TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) |
#define | TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) |
#define | TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) |
#define | TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) |
#define | TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) |
#define | TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) |
#define | TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) |
#define | TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) |
#define | TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) |
#define | TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) |
#define | TSPI_NEGATE_1 ((uint32_t)0x00000000) |
#define | TSPI_NEGATE_2 ((uint32_t)0x00000001) |
#define | TSPI_NEGATE_3 ((uint32_t)0x00000002) |
#define | TSPI_NEGATE_4 ((uint32_t)0x00000003) |
#define | TSPI_NEGATE_5 ((uint32_t)0x00000004) |
#define | TSPI_NEGATE_6 ((uint32_t)0x00000005) |
#define | TSPI_NEGATE_7 ((uint32_t)0x00000006) |
#define | TSPI_NEGATE_8 ((uint32_t)0x00000007) |
#define | TSPI_NEGATE_9 ((uint32_t)0x00000008) |
#define | TSPI_NEGATE_10 ((uint32_t)0x00000009) |
#define | TSPI_NEGATE_11 ((uint32_t)0x0000000a) |
#define | TSPI_NEGATE_12 ((uint32_t)0x0000000b) |
#define | TSPI_NEGATE_13 ((uint32_t)0x0000000c) |
#define | TSPI_NEGATE_14 ((uint32_t)0x0000000d) |
#define | TSPI_NEGATE_15 ((uint32_t)0x0000000e) |
#define | TSPI_NEGATE_16 ((uint32_t)0x0000000f) |
#define | TSPI_PARITY_DISABLE ((uint32_t)0x00000000) |
#define | TSPI_PARITY_ENABLE ((uint32_t)0x00000002) |
#define | TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) |
#define | TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) |
#define | TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) |
#define | TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) |
#define | TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) |
#define | TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) |
#define | TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) |
#define | TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) |
#define | TSPI_TX_DONE ((uint32_t)0x00400000) |
#define | TSPI_TX_DONE_CLR ((uint32_t)0x00400000) |
#define | TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) |
#define | TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) |
#define | TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) |
#define | TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) |
#define | TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) |
#define | TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) |
#define | TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) |
#define | TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) |
#define | TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) |
#define | TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) |
#define | TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) |
#define | TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) |
#define | TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) |
#define | TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) |
#define | TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) |
#define | TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) |
#define | TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) |
#define | TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) |
#define | TSPI_RX_DONE ((uint32_t)0x00000040) |
#define | TSPI_RX_DONE_CLR ((uint32_t)0x00000040) |
#define | TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) |
#define | TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) |
#define | TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) |
#define | TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) |
#define | TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) |
#define | TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) |
#define | TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) |
#define | TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) |
#define | TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) |
#define | TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) |
#define | TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) |
#define | TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) |
#define | TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) |
#define | TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) |
#define | TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) |
#define | TSPI_TRGERR_ERR ((uint32_t)0x00000008) |
#define | TSPI_TRGERR_MASK ((uint32_t)0x00000008) |
#define | TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) |
#define | TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) |
#define | TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) |
#define | TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) |
#define | TSPI_OVERRUN_ERR ((uint32_t)0x00000002) |
#define | TSPI_OVERRUN_MASK ((uint32_t)0x00000002) |
#define | TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) |
#define | TSPI_PARITY_ERR ((uint32_t)0x00000001) |
#define | TSPI_PARITY_MASK ((uint32_t)0x00000001) |
#define | TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) |
#define | TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) |
#define | TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) |
#define | TSPI_FIFO_MAX ((uint32_t)0x00000008) |
#define | NOERROR ((uint32_t)0x00000000) |
#define | TIMEOUTERR ((uint32_t)0x00000001) |
#define | DATALENGTHERR ((uint32_t)0x00000002) |
#define | DATABUFEMPERR ((uint32_t)0x00000003) |
#define | DATALACKERR ((uint32_t)0x00000004) |
#define | FIFOFULLERR ((uint32_t)0x00000005) |
#define | TRANSMITMODEERR ((uint32_t)0x00000006) |
#define | UNDERRUNERR ((uint32_t)0x00000007) |
#define | OVERRUNERR ((uint32_t)0x00000008) |
#define | PARITYERR ((uint32_t)0x00000009) |
#define | INITERR ((uint32_t)0x000000) |
#define | BUFFSIZE ((uint32_t)0x000000010 |
Typedefs | |
typedef struct tspi_handle | tspi_t |
TSPI handle structure definition. More... | |
Functions | |
TXZ_Result | tspi_init (tspi_t *p_obj) |
TXZ_Result | tspi_deinit (tspi_t *p_obj) |
TXZ_Result | tspi_format (tspi_t *p_obj) |
TXZ_Result | tspi_master_write (tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout) |
TXZ_Result | tspi_master_read (tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout) |
TXZ_Result | tspi_master_transfer (tspi_t *p_obj, tspi_transmit_t *p_info) |
TXZ_Result | tspi_master_receive (tspi_t *p_obj, tspi_receive_t *p_info) |
TXZ_Result | tspi_master_dma_transfer (tspi_t *p_obj, tspi_transmit_t *p_info) |
TXZ_Result | tspi_master_dma_receive (tspi_t *p_obj, tspi_receive_t *p_info) |
void | tspi_irq_handler_transmit (tspi_t *p_obj) |
void | tspi_irq_handler_receive (tspi_t *p_obj) |
void | tspi_error_irq_handler (tspi_t *p_obj) |
TXZ_Result | tspi_get_status (tspi_t *p_obj, uint32_t *p_status) |
TXZ_Result | tspi_get_error (tspi_t *p_obj, uint32_t *p_error) |
TXZ_Result | tspi_error_clear (tspi_t *p_obj) |
TXZ_Result | tspi_discard_transmit (tspi_t *p_obj) |
TXZ_Result | tspi_discard_receive (tspi_t *p_obj) |
This file provides all the functions prototypes for TSPI driver.
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Copyright(C) Toshiba Electronic Device Solutions Corporation 2019