51 #define TSPI_NULL ((void *)0) 61 #define TSPI_PARAM_OK ((int32_t)1) 62 #define TSPI_PARAM_NG ((int32_t)0) 72 #define TSPI_RESULT_SUCCESS (0) 73 #define TSPI_RESULT_FAILURE (-1) 83 #define TSPI_RESET10 ((uint32_t)0x00000080) 84 #define TSPI_RESET01 ((uint32_t)0x00000040) 95 #define TSPI_DISABLE ((uint32_t)0x00000000) 96 #define TSPI_ENABLE ((uint32_t)0x00000001) 106 #define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) 107 #define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) 117 #define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) 118 #define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) 119 #define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) 129 #define TSPI_SPI_MODE ((uint32_t)0x00000000) 130 #define TSPI_SIO_MODE ((uint32_t)0x00002000) 141 #define TSPI_MASTER_OPEARTION ((uint32_t)0x00001000) 142 #define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) 153 #define TSPI_TX_ONLY ((uint32_t)0x00000400) 154 #define TSPI_RX_ONLY ((uint32_t)0x00000800) 155 #define TSPI_TWO_WAY ((uint32_t)0x00000C00) 156 #define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) 167 #define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) 168 #define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) 169 #define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) 170 #define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) 180 #define TSPI_TRANS_RANGE_SINGLE ((uint32_t)0x00000000) 181 #define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) 190 #define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) 191 #define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) 192 #define TSPI_TIDLE_LOW ((uint32_t)0x00800000) 193 #define TSPI_TIDLE_HI ((uint32_t)0x00C00000) 203 #define TSPI_RXDLY_40MHz_OVER ((uint32_t)0x00010000) 204 #define TSPI_RXDLY_40MHz_OR_LESS ((uint32_t)0x00000000) 215 #define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) 216 #define TSPI_TXDEMP_HI ((uint32_t)0x00200000) 227 #define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) 228 #define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) 229 #define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) 230 #define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) 231 #define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) 232 #define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) 233 #define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) 234 #define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) 235 #define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) 246 #define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) 247 #define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) 248 #define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) 249 #define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) 250 #define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) 251 #define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) 252 #define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) 253 #define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) 254 #define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000700) 265 #define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) 266 #define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) 277 #define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) 278 #define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) 289 #define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) 290 #define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) 301 #define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) 302 #define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) 313 #define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) 314 #define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) 325 #define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) 326 #define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) 327 #define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) 338 #define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) 339 #define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) 340 #define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) 351 #define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) 352 #define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) 363 #define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) 364 #define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) 375 #define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) 376 #define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) 377 #define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) 378 #define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) 379 #define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) 380 #define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) 381 #define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) 382 #define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) 383 #define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) 384 #define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) 395 #define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) 396 #define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) 397 #define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) 398 #define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) 399 #define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) 400 #define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) 401 #define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) 402 #define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) 403 #define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) 404 #define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) 405 #define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) 406 #define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) 407 #define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) 408 #define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) 409 #define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) 410 #define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) 421 #define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) 422 #define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) 433 #define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) 434 #define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) 435 #define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) 436 #define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) 437 #define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) 438 #define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) 439 #define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) 440 #define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) 441 #define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) 442 #define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) 443 #define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) 444 #define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) 445 #define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) 446 #define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) 447 #define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) 448 #define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) 449 #define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) 450 #define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) 451 #define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) 452 #define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) 453 #define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) 454 #define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) 455 #define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) 456 #define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) 457 #define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) 458 #define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) 469 #define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) 470 #define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) 471 #define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) 472 #define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) 473 #define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) 474 #define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) 475 #define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) 476 #define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) 477 #define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) 478 #define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) 479 #define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) 480 #define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) 481 #define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) 482 #define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) 483 #define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) 484 #define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) 495 #define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) 496 #define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) 507 #define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) 508 #define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) 519 #define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) 520 #define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) 531 #define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) 532 #define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) 543 #define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) 544 #define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) 555 #define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) 556 #define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) 567 #define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) 568 #define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) 569 #define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) 570 #define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) 571 #define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) 572 #define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) 573 #define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) 574 #define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) 575 #define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) 576 #define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) 577 #define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) 578 #define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) 579 #define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) 580 #define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) 581 #define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) 592 #define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) 593 #define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) 594 #define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) 595 #define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) 596 #define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) 597 #define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) 598 #define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) 599 #define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) 600 #define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) 601 #define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) 602 #define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) 603 #define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) 604 #define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) 605 #define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) 606 #define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) 607 #define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) 618 #define TSPI_NEGATE_1 ((uint32_t)0x00000000) 619 #define TSPI_NEGATE_2 ((uint32_t)0x00000001) 620 #define TSPI_NEGATE_3 ((uint32_t)0x00000002) 621 #define TSPI_NEGATE_4 ((uint32_t)0x00000003) 622 #define TSPI_NEGATE_5 ((uint32_t)0x00000004) 623 #define TSPI_NEGATE_6 ((uint32_t)0x00000005) 624 #define TSPI_NEGATE_7 ((uint32_t)0x00000006) 625 #define TSPI_NEGATE_8 ((uint32_t)0x00000007) 626 #define TSPI_NEGATE_9 ((uint32_t)0x00000008) 627 #define TSPI_NEGATE_10 ((uint32_t)0x00000009) 628 #define TSPI_NEGATE_11 ((uint32_t)0x0000000a) 629 #define TSPI_NEGATE_12 ((uint32_t)0x0000000b) 630 #define TSPI_NEGATE_13 ((uint32_t)0x0000000c) 631 #define TSPI_NEGATE_14 ((uint32_t)0x0000000d) 632 #define TSPI_NEGATE_15 ((uint32_t)0x0000000e) 633 #define TSPI_NEGATE_16 ((uint32_t)0x0000000f) 644 #define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) 645 #define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) 656 #define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) 657 #define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) 668 #define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) 669 #define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) 680 #define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) 681 #define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) 682 #define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) 693 #define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) 694 #define TSPI_TX_DONE ((uint32_t)0x00400000) 695 #define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) 706 #define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) 707 #define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) 708 #define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) 718 #define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) 719 #define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) 729 #define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) 730 #define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) 731 #define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) 732 #define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) 733 #define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) 734 #define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) 735 #define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) 736 #define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) 737 #define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) 748 #define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) 749 #define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) 750 #define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) 761 #define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) 762 #define TSPI_RX_DONE ((uint32_t)0x00000040) 763 #define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) 774 #define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) 775 #define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) 776 #define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) 786 #define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) 787 #define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) 798 #define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) 799 #define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) 800 #define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) 801 #define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) 802 #define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) 803 #define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) 804 #define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) 805 #define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) 806 #define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) 817 #define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) 818 #define TSPI_TRGERR_ERR ((uint32_t)0x00000008) 819 #define TSPI_TRGERR_MASK ((uint32_t)0x00000008) 829 #define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) 830 #define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) 831 #define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) 841 #define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) 842 #define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) 843 #define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) 854 #define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) 855 #define TSPI_PARITY_ERR ((uint32_t)0x00000001) 856 #define TSPI_PARITY_MASK ((uint32_t)0x00000001) 866 #define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) 867 #define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) 868 #define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) 878 #define TSPI_FIFO_MAX ((uint32_t)0x00000008) 888 #define NOERROR ((uint32_t)0x00000000) 889 #define TIMEOUTERR ((uint32_t)0x00000001) 890 #define DATALENGTHERR ((uint32_t)0x00000002) 891 #define DATABUFEMPERR ((uint32_t)0x00000003) 892 #define DATALACKERR ((uint32_t)0x00000004) 893 #define FIFOFULLERR ((uint32_t)0x00000005) 894 #define TRANSMITMODEERR ((uint32_t)0x00000006) 895 #define UNDERRUNERR ((uint32_t)0x00000007) 896 #define OVERRUNERR ((uint32_t)0x00000008) 897 #define PARITYERR ((uint32_t)0x00000009) 898 #define INITERR ((uint32_t)0x000000) 908 #define BUFFSIZE ((uint32_t)0x000000010 uint32_t txdemp
Definition: txz_tspi.h:1070
uint32_t rffll
Definition: txz_tspi.h:1198
uint32_t fint
Definition: txz_tspi.h:1134
uint32_t tspisue
Definition: txz_tspi.h:1180
uint32_t trxe
Definition: txz_tspi.h:1046
TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout)
Transmit data..
Definition: txz_tspi.c:1397
uint32_t inttxfe
Definition: txz_tspi.h:1078
uint32_t reserved
Definition: txz_tspi.h:1164
uint32_t rffllclr
Definition: txz_tspi.h:1104
tspi_control2_t cnt2
Definition: txz_tspi.h:1232
uint32_t til
Definition: txz_tspi.h:1074
Format control1.
Definition: txz_tspi.h:1162
uint32_t cs0pol
Definition: txz_tspi.h:1142
TSPI handle structure definenition.
Definition: txz_tspi.h:1249
uint32_t trgen
Definition: txz_tspi.h:1044
Format control0.
Definition: txz_tspi.h:1128
Receive event information structure definenition.
Definition: txz_tspi.h:966
uint32_t ovrerr
Definition: txz_tspi.h:1214
tspi_baudrate_t brd
Definition: txz_tspi.h:1236
uint32_t tidle
Definition: txz_tspi.h:1068
uint32_t brs
Definition: txz_tspi.h:1118
tspi_transmit16_t tx16
Definition: txz_tspi.h:1032
Transmit data information structure definenition.
Definition: txz_tspi.h:1017
TSB_TSPI_TypeDef * p_instance
Definition: txz_tspi.h:1251
tspi_initial_setting_t init
Definition: txz_tspi.h:1252
uint32_t errcode
Definition: txz_tspi.h:1253
uint32_t inttxwe
Definition: txz_tspi.h:1080
tspi_transmit8_t tx8
Definition: txz_tspi.h:1031
struct tspi_handle tspi_t
TSPI handle structure definenition.
Receive event information structure definenition.
Definition: txz_tspi.h:954
Receive event information structure definenition.
Definition: txz_tspi.h:978
uint8_t * p_data
Definition: txz_tspi.h:994
tspi_control1_t cnt1
Definition: txz_tspi.h:1230
uint32_t csint
Definition: txz_tspi.h:1148
uint16_t * p_data
Definition: txz_tspi.h:956
TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error)
Get error information.
Definition: txz_tspi.c:2369
Clock setting structure definenition.
Definition: txz_tspi.h:1114
uint32_t tlvll
Definition: txz_tspi.h:1190
TXZ_Result tspi_error_clear(tspi_t *p_obj)
Error information clear.
Definition: txz_tspi.c:2403
uint32_t cs1pol
Definition: txz_tspi.h:1140
tspi_fmtr1_t fmr1
Definition: txz_tspi.h:1240
Receive event information structure definenition.
Definition: txz_tspi.h:941
void tspi_irq_handler_receive(tspi_t *p_obj)
IRQ Handler for receive.
Definition: txz_tspi.c:2056
uint32_t rp
Definition: txz_tspi.h:1261
uint32_t num
Definition: txz_tspi.h:957
Control Setting structure definenition.
Definition: txz_tspi.h:1100
uint32_t udrerr
Definition: txz_tspi.h:1212
uint32_t inttxwf
Definition: txz_tspi.h:1186
uint32_t tfemp
Definition: txz_tspi.h:1188
uint32_t fl
Definition: txz_tspi.h:1132
uint32_t intrxff
Definition: txz_tspi.h:1196
struct tspi_handle::@2 receive
Receive Informatin.
Transmit data information structure definenition.
Definition: txz_tspi.h:1029
uint32_t txrun
Definition: txz_tspi.h:1182
uint32_t dmate
Definition: txz_tspi.h:1088
Control Setting structure definenition.
Definition: txz_tspi.h:1066
uint32_t ckpol
Definition: txz_tspi.h:1146
uint32_t num
Definition: txz_tspi.h:1008
uint32_t num
Definition: txz_tspi.h:995
TXZ_Result tspi_discard_transmit(tspi_t *p_obj)
Discard transmit.
Definition: txz_tspi.c:2426
void tspi_irq_handler_transmit(tspi_t *p_obj)
IRQ Handler for transmit.
Definition: txz_tspi.c:1886
uint32_t intrxfe
Definition: txz_tspi.h:1082
uint32_t txend
Definition: txz_tspi.h:1184
uint32_t perr
Definition: txz_tspi.h:1216
Initial setting structure definenition.
Definition: txz_tspi.h:1227
uint32_t sckcsdl
Definition: txz_tspi.h:1152
uint32_t cs3pol
Definition: txz_tspi.h:1136
void(* handler)(uint32_t id, TXZ_Result result)
Definition: txz_tspi.h:1264
uint32_t rxrun
Definition: txz_tspi.h:1192
uint32_t vpm
Definition: txz_tspi.h:1168
tspi_fmtr0_t fmr0
Definition: txz_tspi.h:1238
uint32_t ril
Definition: txz_tspi.h:1076
Status register.
Definition: txz_tspi.h:1178
All common macro and definition for TXZ peripheral drivers.
uint32_t mstr
Definition: txz_tspi.h:1050
Control Setting structure definenition.
Definition: txz_tspi.h:1042
TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info)
Transmit data. Non-Blocking Communication.
Definition: txz_tspi.c:1636
Transmit data information structure definenition.
Definition: txz_tspi.h:1005
uint32_t tspims
Definition: txz_tspi.h:1048
TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status)
Get status.
Definition: txz_tspi.c:2332
TXZ_Result tspi_format(tspi_t *p_obj)
Data Format setting.
Definition: txz_tspi.c:2269
struct tspi_handle::@1 transmit
Transmit Informatin.
tspi_receive_t info
Definition: txz_tspi.h:1273
uint32_t tmmd
Definition: txz_tspi.h:1052
uint32_t num
Definition: txz_tspi.h:1020
uint8_t tx_allign
Definition: txz_tspi.h:1263
TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout)
Receive data. Blocking Communication.
Definition: txz_tspi.c:1528
TXZ_Result tspi_deinit(tspi_t *p_obj)
Release the TSPI object.
Definition: txz_tspi.c:1370
uint32_t tfempclr
Definition: txz_tspi.h:1102
void tspi_error_irq_handler(tspi_t *p_obj)
IRQ Handler for error.
Definition: txz_tspi.c:2178
Transmit data information structure definenition.
Definition: txz_tspi.h:992
uint32_t brck
Definition: txz_tspi.h:1116
uint32_t cssel
Definition: txz_tspi.h:1054
uint32_t dir
Definition: txz_tspi.h:1130
uint32_t cs2pol
Definition: txz_tspi.h:1138
tspi_transmit32_t tx32
Definition: txz_tspi.h:1033
uint32_t cssckdl
Definition: txz_tspi.h:1150
tspi_receive8_t rx8
Definition: txz_tspi.h:980
uint32_t rlvl
Definition: txz_tspi.h:1200
TXZ_Result tspi_discard_receive(tspi_t *p_obj)
Discard receive.
Definition: txz_tspi.c:2486
tspi_transmit_t info
Definition: txz_tspi.h:1262
uint32_t * p_data
Definition: txz_tspi.h:1019
uint16_t * p_data
Definition: txz_tspi.h:1007
TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info)
Receive data. Non-Blocking Communication.
Definition: txz_tspi.c:1801
uint32_t intrxwe
Definition: txz_tspi.h:1084
uint32_t rxdly
Definition: txz_tspi.h:1072
uint32_t id
Definition: txz_tspi.h:1229
uint32_t fc
Definition: txz_tspi.h:1056
TXZ_Result tspi_init(tspi_t *p_obj)
Initialize the TSPI object.
Definition: txz_tspi.c:1273
uint8_t rx_allign
Definition: txz_tspi.h:1274
tspi_control3_t cnt3
Definition: txz_tspi.h:1234
uint32_t vpe
Definition: txz_tspi.h:1166
uint32_t num
Definition: txz_tspi.h:969
uint32_t rxend
Definition: txz_tspi.h:1194
uint32_t interr
Definition: txz_tspi.h:1086
uint32_t num
Definition: txz_tspi.h:944
uint32_t * p_data
Definition: txz_tspi.h:968
uint8_t * p_data
Definition: txz_tspi.h:943
tspi_receive16_t rx16
Definition: txz_tspi.h:981
uint32_t dmare
Definition: txz_tspi.h:1090
uint32_t ckpha
Definition: txz_tspi.h:1144
tspi_receive32_t rx32
Definition: txz_tspi.h:982
Error flag.
Definition: txz_tspi.h:1210