TMPM4KxA Group Peripheral Driver User Manual  V1.0.4.0
txz_t32a.h
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1 
13 /*------------------------------------------------------------------------------*/
14 /* Define to prevent recursive inclusion */
15 /*------------------------------------------------------------------------------*/
16 #ifndef __T32A_H
17 #define __T32A_H
18 
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22 
23 /*------------------------------------------------------------------------------*/
24 /* Includes */
25 /*------------------------------------------------------------------------------*/
26 #include "txz_driver_def.h"
37 /*------------------------------------------------------------------------------*/
38 /* Macro Definition */
39 /*------------------------------------------------------------------------------*/
50 #define T32A_RESULT_SUCCESS (0)
51 #define T32A_RESULT_FAILURE (-1)
52 #define T32A_READ_FAILURE (0xFFFFFFFF) /* End of group T32A_Result */
56 
62 #define T32A_NULL ((void *)0) /* End of group T32A_NullPointer */
66 
72 #define T32A_DBG_HALT_RUN ((uint32_t)0x00000000)
73 #define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) /* End of group T32A_HALT */
77 
83 #define T32A_MODE_16 ((uint32_t)0x00000000)
84 #define T32A_MODE_32 ((uint32_t)0x00000001) /* End of group T32A_MODE32 */
88 
94 #define T32A_RUNFLG_RUN ((uint32_t)0x00000010)
95 #define T32A_RUNFLG_STOP ((uint32_t)0x00000000) /* End of group T32A_RUNFLGx */
99 
105 #define T32A_COUNT_DONT_STOP ((uint32_t)0x0000000)
106 #define T32A_COUNT_STOP ((uint32_t)0x0000004) /* End of group T32A_SFTSTPx */
110 
116 #define T32A_COUNT_DONT_START ((uint32_t)0x0000000)
117 #define T32A_COUNT_START ((uint32_t)0x0000002) /* End of group T32A_SFTSTAx */
121 
127 #define T32A_RUN_DISABLE ((uint32_t)0x00000000)
128 #define T32A_RUN_ENABLE ((uint32_t)0x00000001) /* End of group T32A_RUNx */
132 
133 
139 #define T32A_PRSCLx_1 ((uint32_t)0x00000000)
140 #define T32A_PRSCLx_2 ((uint32_t)0x10000000)
141 #define T32A_PRSCLx_8 ((uint32_t)0x20000000)
142 #define T32A_PRSCLx_32 ((uint32_t)0x30000000)
143 #define T32A_PRSCLx_128 ((uint32_t)0x40000000)
144 #define T32A_PRSCLx_256 ((uint32_t)0x50000000)
145 #define T32A_PRSCLx_512 ((uint32_t)0x60000000)
146 #define T32A_PRSCLx_1024 ((uint32_t)0x70000000) /* End of group T32A_PRSCLx */
150 
156 #define T32A_CLKx_PRSCLx ((uint32_t)0x00000000)
157 #define T32A_CLKx_INTRG ((uint32_t)0x01000000)
158 #define T32A_CLKx_TIM_RISING_EDGE ((uint32_t)0x02000000)
159 #define T32A_CLKx_TIM_TRAILING_EDGE ((uint32_t)0x03000000)
160 #define T32A_CLKx_EXTTRG_RISING_EDGE ((uint32_t)0x04000000)
161 #define T32A_CLKx_EXTTRG_TRAILING_EDGE ((uint32_t)0x05000000) /* End of group T32A_CLKx */
165 
171 #define T32A_WBF_DISABLE ((uint32_t)0x00000000)
172 #define T32A_WBF_ENABLE ((uint32_t)0x00100000) /* End of group T32A_WBFx */
176 
182 #define T32A_COUNT_UP ((uint32_t)0x00000000)
183 #define T32A_COUNT_DOWN ((uint32_t)0x00010000)
184 #define T32A_COUNT_UPDOWN ((uint32_t)0x00020000)
185 #define T32A_COUNT_PLS ((uint32_t)0x00030000) /* End of group T32A_UPDNx */
189 
195 #define T32A_RELOAD_NON ((uint32_t)0x00000000)
196 #define T32A_RELOAD_INTRG ((uint32_t)0x00000100)
197 #define T32A_RELOAD_EXTTRG_RISING_EDGE ((uint32_t)0x00000200)
198 #define T32A_RELOAD_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000300)
199 #define T32A_RELOAD_TIM_RISING_EDGE ((uint32_t)0x00000400)
200 #define T32A_RELOAD_TIM_TRAILING_EDGE ((uint32_t)0x00000500)
201 #define T32A_RELOAD_SYNC ((uint32_t)0x00000600)
202 #define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /* End of group T32A_RELDx */
206 
212 #define T32A_STOP_NON ((uint32_t)0x00000000)
213 #define T32A_STOP_INTRG ((uint32_t)0x00000010)
214 #define T32A_STOP_EXTTRG_RISING_EDGE ((uint32_t)0x00000020)
215 #define T32A_STOP_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000030)
216 #define T32A_STOP_TIM_RISING_EDGE ((uint32_t)0x00000040)
217 #define T32A_STOP_TIM_TRAILING_EDGE ((uint32_t)0x00000050)
218 #define T32A_STOP_SYNC ((uint32_t)0x00000060)
219 #define T32A_STOP_TREGx ((uint32_t)0x00000070) /* End of group T32A_STOPx */
223 
224 
230 #define T32A_START_NON ((uint32_t)0x00000000)
231 #define T32A_START_INTRG ((uint32_t)0x00000001)
232 #define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002)
233 #define T32A_START_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000003)
234 #define T32A_START_TIM_RISING_EDGE ((uint32_t)0x00000004)
235 #define T32A_START_TIM_TRAILING_EDGE ((uint32_t)0x00000005)
236 #define T32A_START_SYNC ((uint32_t)0x00000006)
237 #define T32A_START_Rsvd ((uint32_t)0x00000007) /* End of group T32A_STARTx */
241 
247 #define T32A_OCR_DISABLE ((uint32_t)0x00000000)
248 #define T32A_OCR_SET ((uint32_t)0x00000001)
249 #define T32A_OCR_CLR ((uint32_t)0x00000002)
250 #define T32A_OCR_INVERSION ((uint32_t)0x00000003) /* End of group T32A_OCRx */
254 
260 #define T32A_OCRCAPx1_DISABLE ((uint32_t)0x00000000)
261 #define T32A_OCRCAPx1_SET ((uint32_t)0x00000040)
262 #define T32A_OCRCAPx1_CLR ((uint32_t)0x00000080)
263 #define T32A_OCRCAPx1_INVERSION ((uint32_t)0x000000C0) /* End of group T32A_OCRCAPx1 */
267 
273 #define T32A_OCRCAPx0_DISABLE ((uint32_t)0x00000000)
274 #define T32A_OCRCAPx0_SET ((uint32_t)0x00000010)
275 #define T32A_OCRCAPx0_CLR ((uint32_t)0x00000020)
276 #define T32A_OCRCAPx0_INVERSION ((uint32_t)0x00000030) /* End of group T32A_OCRCAPx0 */
280 
286 #define T32A_OCRCMPx1_DISABLE ((uint32_t)0x00000000)
287 #define T32A_OCRCMPx1_SET ((uint32_t)0x00000004)
288 #define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008)
289 #define T32A_OCRCMPx1_INVERSION ((uint32_t)0x0000000C) /* End of group T32A_OCRCMPx1 */
293 
299 #define T32A_OCRCMPx0_DISABLE ((uint32_t)0x00000000)
300 #define T32A_OCRCMPx0_SET ((uint32_t)0x00000001)
301 #define T32A_OCRCMPx0_CLR ((uint32_t)0x00000002)
302 #define T32A_OCRCMPx0_INVERSION ((uint32_t)0x00000003) /* End of group T32A_OCRCMPx0 */
306 
312 #define T32A_RGx0_MASK ((uint32_t)0x0000FFFF)
313 #define T32A_RGC0_MASK ((uint32_t)0xFFFFFFFF) /* End of group T32A_RGx0 */
317 
323 #define T32A_RGx1_MASK ((uint32_t)0x0000FFFF)
324 #define T32A_RGC1_MASK ((uint32_t)0xFFFFFFFF) /* End of group T32A_RGx0 */
328 
334 #define T32A_TMRx_MASK ((uint32_t)0x0000FFFF)
335 #define T32A_TMRC_MASK ((uint32_t)0xFFFFFFFF) /* End of group T32A_TMRx */
339 
345 #define T32A_RELDx_MASK ((uint32_t)0x0000FFFF)
346 #define T32A_RELDC_MASK ((uint32_t)0xFFFFFFFF) /* End of group T32A_RELD */
350 
356 #define T32A_CAPMx1_DISABLE ((uint32_t)0x00000000)
357 #define T32A_CAPMx1_INTRG ((uint32_t)0x00000010)
358 #define T32A_CAPMx1_INx0_RISING_EDGE ((uint32_t)0x00000020)
359 #define T32A_CAPMx1_INx0_TRAILING_EDGE ((uint32_t)0x00000030)
360 #define T32A_CAPMx1_INx1_RISING_EDGE ((uint32_t)0x00000040)
361 #define T32A_CAPMx1_INx1_TRAILING_EDGE ((uint32_t)0x00000050)
362 #define T32A_CAPMx1_TIM_RISING_EDGE ((uint32_t)0x00000060)
363 #define T32A_CAPMx1_TIM_TRAILING_EDGE ((uint32_t)0x00000070) /* End of group T32A_CAPMx1 */
367 
373 #define T32A_CAPMx0_DISABLE ((uint32_t)0x00000000)
374 #define T32A_CAPMx0_INTRG ((uint32_t)0x00000001)
375 #define T32A_CAPMx0_INx0_RISING_EDGE ((uint32_t)0x00000002)
376 #define T32A_CAPMx0_INx0_TRAILING_EDGE ((uint32_t)0x00000003)
377 #define T32A_CAPMx0_INx1_RISING_EDGE ((uint32_t)0x00000004)
378 #define T32A_CAPMx0_INx1_TRAILING_EDGE ((uint32_t)0x00000005)
379 #define T32A_CAPMx0_TIM_RISING_EDGE ((uint32_t)0x00000006)
380 #define T32A_CAPMx0_TIM_TRAILING_EDGE ((uint32_t)0x00000007) /* End of group T32A_CAPMx0 */
384 
390 #define T32A_CAPx0_MASK ((uint32_t)0x0000FFFF)
391 #define T32A_CAPC0_MASK ((uint32_t)0xFFFFFFFF) /* End of group T32A_CAPx0 */
395 
401 #define T32A_CAPx1_MASK ((uint32_t)0x0000FFFF)
402 #define T32A_CAPC1_MASK ((uint32_t)0xFFFFFFFF) /* End of group T32A_CAPx1 */
406 
412 #define T32A_IMSTERR_MASK_NOREQ ((uint32_t)0x00000000)
413 #define T32A_IMSTERR_MASK_REQ ((uint32_t)0x00000010)
414  /* End of group T32A_IMSTERR */
417 
423 #define T32A_IMUFx_MASK_NOREQ ((uint32_t)0x00000000)
424 #define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) /* End of group T32A_IMUFx */
428 
434 #define T32A_IMOFx_MASK_NOREQ ((uint32_t)0x00000000)
435 #define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) /* End of group T32A_IMOFx */
439 
445 #define T32A_IMx1_MASK_NOREQ ((uint32_t)0x00000000)
446 #define T32A_IMx1_MASK_REQ ((uint32_t)0x00000002) /* End of group T32A_IMx1 */
450 
456 #define T32A_IMx0_MASK_NOREQ ((uint32_t)0x00000000)
457 #define T32A_IMx0_MASK_REQ ((uint32_t)0x00000001) /* End of group T32A_IMx0 */
461 
467 #define T32A_INTSTERR_FLG_MASK ((uint32_t)0x00000010)
468 #define T32A_INTSTERR_FLG_CLR ((uint32_t)0x00000010)
469  /* End of group T32A_INTSTERR */
472 
478 #define T32A_INTUFx_FLG_MASK ((uint32_t)0x00000008)
479 #define T32A_INTUFx_FLG_CLR ((uint32_t)0x00000008) /* End of group T32A_INTUFA */
483 
489 #define T32A_INTOFx_FLG_MASK ((uint32_t)0x00000004)
490 #define T32A_INTOFx_FLG_CLR ((uint32_t)0x00000004) /* End of group T32A_INTOFA */
494 
500 #define T32A_INTx1_FLG_MASK ((uint32_t)0x00000002)
501 #define T32A_INTx1_FLG_CLR ((uint32_t)0x00000002) /* End of group T32A_INTA1 */
505 
511 #define T32A_INTx0_FLG_MASK ((uint32_t)0x00000001)
512 #define T32A_INTx0_FLG_CLR ((uint32_t)0x00000001) /* End of group T32A_INTA0 */
516 
522 #define T32A_DMAENx2_DISABLE ((uint32_t)0x00000000)
523 #define T32A_DMAENx2_ENABLE ((uint32_t)0x00000004) /* End of group T32A_DMAENx2 */
527 
533 #define T32A_DMAENx1_DISABLE ((uint32_t)0x00000000)
534 #define T32A_DMAENx1_ENABLE ((uint32_t)0x00000002) /* End of group T32A_DMAENx1 */
538 
544 #define T32A_DMAENx0_DISABLE ((uint32_t)0x00000000)
545 #define T32A_DMAENx0_ENABLE ((uint32_t)0x00000001) /* End of group T32A_DMAENx0 */
549 
555 #define T32A_PDN_NON0 ((uint32_t)0x00000000)
556 #define T32A_PDN_NON1 ((uint32_t)0x00001000)
557 #define T32A_PDN_INC0_RISING_EDGE ((uint32_t)0x00002000)
558 #define T32A_PDN_INC0_TRAILING_EDGE ((uint32_t)0x00003000)
559 #define T32A_PDN_INC1_RISING_EDGE ((uint32_t)0x00004000)
560 #define T32A_PDN_INC1_TRAILING_EDGE ((uint32_t)0x00005000)
561 #define T32A_PDN_INC0_BOTH_EDGE ((uint32_t)0x00006000)
562 #define T32A_PDN_INC1_BOTH_EDGE ((uint32_t)0x00007000) /* End of group T32A_PDN */
566 
572 #define T32A_PUP_NON0 ((uint32_t)0x00000000)
573 #define T32A_PUP_NON1 ((uint32_t)0x00000100)
574 #define T32A_PUP_INC0_RISING_EDGE ((uint32_t)0x00000200)
575 #define T32A_PUP_INC0_TRAILING_EDGE ((uint32_t)0x00000300)
576 #define T32A_PUP_INC1_RISING_EDGE ((uint32_t)0x00000400)
577 #define T32A_PUP_INC1_TRAILING_EDGE ((uint32_t)0x00000500)
578 #define T32A_PUP_INC0_BOTH_EDGE ((uint32_t)0x00000600)
579 #define T32A_PUP_INC1_BOTH_EDGE ((uint32_t)0x00000700) /* End of group T32A_PUP */
583 
589 #define T32A_NF_NON ((uint32_t)0x00000000)
590 #define T32A_NF_2 ((uint32_t)0x00000010)
591 #define T32A_NF_4 ((uint32_t)0x00000020)
592 #define T32A_NF_8 ((uint32_t)0x00000030) /* End of group T32A_NF */
596 
602 #define T32A_PDIR_FORWARD ((uint32_t)0x00000000)
603 #define T32A_PDIR_BACKWARD ((uint32_t)0x00000002) /* End of group T32A_PDIR */
607 
613 #define T32A_PMODE_PHASE_2 ((uint32_t)0x00000000)
614 #define T32A_PMODE_PHASE_1 ((uint32_t)0x00000001) /* End of group T32A_PMODE */
618  /* End of group T32A_Exported_define */
622 
623 /*------------------------------------------------------------------------------*/
624 /* Enumerated Type Definition */
625 /*------------------------------------------------------------------------------*/
634 typedef enum
635 {
639  T32A_TIMERMAX,
640 }t32_type_t;
641 
646 typedef enum
647 {
648  T32A_REG0 = 0,
651 }t32_regnum_t;
656 typedef enum
657 {
663 }t32_mode_t;
664 
669 typedef enum
670 {
676 }t32_triger_t; /* End of group T32A_Exported_Typedef */
680 
681 /*------------------------------------------------------------------------------*/
682 /* Structure Definition */
683 /*------------------------------------------------------------------------------*/
688 /*----------------------------------*/
693 /*----------------------------------*/
694 typedef struct
695 {
696  uint32_t halt;
698  uint32_t mode;
700 } t32a_mode_t;
701 
702 /*----------------------------------*/
707 /*----------------------------------*/
708 typedef struct
709 {
710  uint32_t runflg;
712  uint32_t sftstp;
714  uint32_t sftsta;
716  uint32_t run;
718 } t32a_runx_t;
719 
720 /*----------------------------------*/
725 /*----------------------------------*/
726 typedef struct
727 {
728  uint32_t prscl;
730  uint32_t clk;
732  uint32_t wbf;
734  uint32_t updn;
736  uint32_t reld;
738  uint32_t stop;
740  uint32_t start;
742 } t32a_crx_t;
743 
744 /*----------------------------------*/
749 /*----------------------------------*/
750 typedef struct
751 {
752  uint32_t ocr;
755 
756 /*----------------------------------*/
761 /*----------------------------------*/
762 typedef struct
763 {
764  uint32_t ocrcap1;
766  uint32_t ocrcap0;
768  uint32_t ocrcmp1;
770  uint32_t ocrcmp0;
773 
774 /*----------------------------------*/
779 /*----------------------------------*/
780 typedef struct
781 {
782  uint32_t capmx1;
784  uint32_t capmx0;
786 } t32a_capcrx_t;
787 
788 /*----------------------------------*/
793 /*----------------------------------*/
794 typedef struct
795 {
796  uint32_t rgx0;
798 } t32a_rgx0_t;
799 
800 /*----------------------------------*/
805 /*----------------------------------*/
806 typedef struct
807 {
808  uint32_t rgx1;
810 } t32a_rgx1_t;
811 
812 /*----------------------------------*/
817 /*----------------------------------*/
818 typedef struct
819 {
820  uint32_t tmrx;
822 } t32a_tmrx_t;
823 
824 /*----------------------------------*/
829 /*----------------------------------*/
830 typedef struct
831 {
832  uint32_t reld;
834 } t32a_reldx_t;
835 
836 /*----------------------------------*/
841 /*----------------------------------*/
842 typedef struct
843 {
844  uint32_t capx0;
846 } t32a_capx0_t;
847 
848 /*----------------------------------*/
853 /*----------------------------------*/
854 typedef struct
855 {
856  uint32_t capx1;
858 } t32a_capx1_t;
859 
860 /*----------------------------------*/
865 /*----------------------------------*/
866 typedef struct
867 {
868  uint32_t imsterr;
870  uint32_t imuf;
872  uint32_t imof;
874  uint32_t imx1;
876  uint32_t imx0;
878 } t32a_imx_t;
879 
880 /*----------------------------------*/
885 /*----------------------------------*/
886 typedef struct
887 {
888  uint32_t intsterr;
890  uint32_t intuf;
892  uint32_t intof;
894  uint32_t intx1;
896  uint32_t intx0;
898 } t32a_stx_t;
899 
900 /*----------------------------------*/
905 /*----------------------------------*/
906 typedef struct
907 {
908  uint32_t dmaenx2;
910  uint32_t dmaenx1;
912  uint32_t dmaenx0;
915 
916 /*----------------------------------*/
921 /*----------------------------------*/
922 typedef struct
923 {
924  uint32_t pdn;
926  uint32_t pup;
928  uint32_t nf;
930  uint32_t pdir;
932  uint32_t pmode;
935 
940 /*----------------------------------*/
941 typedef struct
942 {
943  uint32_t id;
958  void (*handler_T)(uint32_t id, uint32_t status, TXZ_Result result);
959  void (*handler_TC0)(uint32_t id, uint32_t status, TXZ_Result result);
960  void (*handler_TC1)(uint32_t id, uint32_t status, TXZ_Result result);
962 
967 /*----------------------------------*/
968 typedef struct
969 {
972 
973 
974 /*----------------------------------*/
978 /*----------------------------------*/
979 typedef struct t32a_handle
980 {
981  TSB_T32A_TypeDef *p_instance;
983  t32a_initial_setting_t init[T32A_TIMERMAX];
984 }t32a_t;
985 
987 /* End of group T32A_Exported_Types */
988 /*------------------------------------------------------------------------------*/
989 /* Functions */
990 /*------------------------------------------------------------------------------*/
995 TXZ_Result t32a_mode_init(t32a_t *p_obj);
996 TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type);
997 TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type);
998 TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type);
999 TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type);
1000 TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type);
1001 TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type);
1002 TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value);
1003 TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val);
1004 TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type);
1005 void t32a_timer_IRQHandler(t32a_t *p_obj);
1006 void t32a_timer_cap0_IRQHandler(t32a_t *p_obj);
1007 void t32a_timer_cap1_IRQHandler(t32a_t *p_obj);
1008 TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl); /* End of group T32A_Exported_functions */
1012  /* End of group T32A */
1016  /* End of group Periph_Driver */
1020 #ifdef __cplusplus
1021 }
1022 #endif /* __cplusplus */
1023 #endif /* __T32A_H */
1024 
t32_regnum_t
Use of Timer register number.
Definition: txz_t32a.h:646
T32A Counter Capture Register A Setting structure definenition.
Definition: txz_t32a.h:818
t32a_outcrx0_t outcrx0
Definition: txz_t32a.h:946
t32a_capx0_t capx0
Definition: txz_t32a.h:953
uint32_t ocrcap1
Definition: txz_t32a.h:764
t32a_rgx0_t rgx0
Definition: txz_t32a.h:949
Definition: txz_t32a.h:674
Definition: txz_t32a.h:648
Capture Control Setting structure definenition.
Definition: txz_t32a.h:780
TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type)
Timer Start in interrupt mode.
Definition: txz_t32a.c:1442
t32a_mode_t mode
Definition: txz_t32a.h:970
uint32_t imof
Definition: txz_t32a.h:872
Status register structure definenition.
Definition: txz_t32a.h:886
T32A Counter Reload Register Setting structure definenition.
Definition: txz_t32a.h:830
Definition: txz_t32a.h:675
uint32_t mode
Definition: txz_t32a.h:698
T32A Capture Register x0 Setting structure definenition.
Definition: txz_t32a.h:854
uint32_t imsterr
Definition: txz_t32a.h:868
T32A Capture Register x0 Setting structure definenition.
Definition: txz_t32a.h:842
Definition: txz_t32a.h:671
uint32_t intuf
Definition: txz_t32a.h:890
uint32_t pdir
Definition: txz_t32a.h:930
t32_type_t
Use of Timer register.
Definition: txz_t32a.h:634
Pulse Count Control register setting structure definenition.
Definition: txz_t32a.h:922
TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val)
Timer Register Value Read.
Definition: txz_t32a.c:1695
TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type)
Timer Stop in interrupt mode.
Definition: txz_t32a.c:1601
t32a_initial_setting_t init[T32A_TIMERMAX]
Definition: txz_t32a.h:983
uint32_t run
Definition: txz_t32a.h:716
uint32_t ocrcmp0
Definition: txz_t32a.h:770
uint32_t pup
Definition: txz_t32a.h:926
Initial Timer setting structure definenition.
Definition: txz_t32a.h:941
T32A Timer Register x1 Setting structure definenition.
Definition: txz_t32a.h:806
uint32_t stop
Definition: txz_t32a.h:738
t32a_runx_t runx
Definition: txz_t32a.h:944
Definition: txz_t32a.h:650
uint32_t dmaenx2
Definition: txz_t32a.h:908
TimerA Mode Setting structure definenition.
Definition: txz_t32a.h:694
TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type)
Timer Start in interrupt mode.
Definition: txz_t32a.c:1543
uint32_t capx0
Definition: txz_t32a.h:844
uint32_t id
Definition: txz_t32a.h:943
T32A Timer Register x0 Setting structure definenition.
Definition: txz_t32a.h:794
TSB_T32A_TypeDef * p_instance
Definition: txz_t32a.h:981
uint32_t capmx1
Definition: txz_t32a.h:782
uint32_t ocr
Definition: txz_t32a.h:752
TXZ_Result t32a_mode_init(t32a_t *p_obj)
Mode Initialize the T32A object.
Definition: txz_t32a.c:1163
uint32_t rgx1
Definition: txz_t32a.h:808
t32_mode_t
Use of Timer register.
Definition: txz_t32a.h:656
Definition: txz_t32a.h:672
Initial Mode setting structure definenition.
Definition: txz_t32a.h:968
uint32_t runflg
Definition: txz_t32a.h:710
t32a_capx1_t capx1
Definition: txz_t32a.h:954
uint32_t capx1
Definition: txz_t32a.h:856
uint32_t imuf
Definition: txz_t32a.h:870
TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type)
Get status.
Definition: txz_t32a.c:1739
Definition: txz_t32a.h:659
t32a_imx_t imx
Definition: txz_t32a.h:955
uint32_t intsterr
Definition: txz_t32a.h:888
t32a_pulse_cr_t pls_cr
Definition: txz_t32a.h:957
uint32_t dmaenx1
Definition: txz_t32a.h:910
uint32_t imx1
Definition: txz_t32a.h:874
Definition: txz_t32a.h:662
TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type)
Timer Stop in interrupt mode.
Definition: txz_t32a.c:1500
struct t32a_handle t32a_t
T32A handle structure definenition.
Counter Register Control Setting structure definenition.
Definition: txz_t32a.h:726
Definition: txz_t32a.h:638
uint32_t rgx0
Definition: txz_t32a.h:796
TimerA Run Control Setting structure definenition.
Definition: txz_t32a.h:708
t32a_reldx_t reldx
Definition: txz_t32a.h:952
uint32_t clk
Definition: txz_t32a.h:730
All common macro and definition for TXZ peripheral drivers.
TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl)
Calculate timer value to set timer register.
Definition: txz_t32a.c:1952
Definition: txz_t32a.h:649
uint32_t prscl
Definition: txz_t32a.h:728
Definition: txz_t32a.h:637
t32a_dma_req_t dma_req
Definition: txz_t32a.h:956
T32A handle structure definenition.
Definition: txz_t32a.h:979
T32AxOUTA Control Setting structure definenition.
Definition: txz_t32a.h:762
uint32_t nf
Definition: txz_t32a.h:928
TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value)
Timer Register Value Setting.
Definition: txz_t32a.c:1646
uint32_t dmaenx0
Definition: txz_t32a.h:912
TimerA Output Control Setting structure definenition.
Definition: txz_t32a.h:750
Definition: txz_t32a.h:673
uint32_t sftstp
Definition: txz_t32a.h:712
Interrupt mask register Setting structure definenition.
Definition: txz_t32a.h:866
uint32_t halt
Definition: txz_t32a.h:696
DMA Request register setting structure definenition.
Definition: txz_t32a.h:906
t32a_rgx1_t rgx1
Definition: txz_t32a.h:950
t32a_tmrx_t tmrx
Definition: txz_t32a.h:951
uint32_t updn
Definition: txz_t32a.h:734
uint32_t pmode
Definition: txz_t32a.h:932
uint32_t ocrcmp1
Definition: txz_t32a.h:768
t32a_capcrx_t capcrx
Definition: txz_t32a.h:948
uint32_t imx0
Definition: txz_t32a.h:876
uint32_t ocrcap0
Definition: txz_t32a.h:766
t32a_initial_mode_t init_mode
Definition: txz_t32a.h:982
TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type)
Initialize the T32A object.
Definition: txz_t32a.c:1193
uint32_t intx0
Definition: txz_t32a.h:896
void t32a_timer_cap0_IRQHandler(t32a_t *p_obj)
IRQ Timer Capture0 Handler for Timer Capture0 interrupt.
Definition: txz_t32a.c:1845
t32_triger_t
Use of Timer register.
Definition: txz_t32a.h:669
uint32_t wbf
Definition: txz_t32a.h:732
uint32_t capmx0
Definition: txz_t32a.h:784
TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type)
Release the T32A object.
Definition: txz_t32a.c:1395
Definition: txz_t32a.h:660
uint32_t tmrx
Definition: txz_t32a.h:820
t32a_outcrx1_t outcrx1
Definition: txz_t32a.h:947
uint32_t reld
Definition: txz_t32a.h:736
Definition: txz_t32a.h:661
uint32_t start
Definition: txz_t32a.h:740
uint32_t pdn
Definition: txz_t32a.h:924
uint32_t sftsta
Definition: txz_t32a.h:714
void t32a_timer_IRQHandler(t32a_t *p_obj)
IRQ Handler for Timer interrupt.
Definition: txz_t32a.c:1790
Definition: txz_t32a.h:658
uint32_t intof
Definition: txz_t32a.h:892
Definition: txz_t32a.h:636
void t32a_timer_cap1_IRQHandler(t32a_t *p_obj)
IRQ Timer Capture1 Handler for Timer Capture1 interrupt.
Definition: txz_t32a.c:1900
uint32_t reld
Definition: txz_t32a.h:832
uint32_t intx1
Definition: txz_t32a.h:894
t32a_crx_t crx
Definition: txz_t32a.h:945