50 #define T32A_RESULT_SUCCESS (0) 51 #define T32A_RESULT_FAILURE (-1) 52 #define T32A_READ_FAILURE (0xFFFFFFFF) 62 #define T32A_NULL ((void *)0) 72 #define T32A_DBG_HALT_RUN ((uint32_t)0x00000000) 73 #define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) 83 #define T32A_MODE_16 ((uint32_t)0x00000000) 84 #define T32A_MODE_32 ((uint32_t)0x00000001) 94 #define T32A_RUNFLG_RUN ((uint32_t)0x00000010) 95 #define T32A_RUNFLG_STOP ((uint32_t)0x00000000) 105 #define T32A_COUNT_DONT_STOP ((uint32_t)0x0000000) 106 #define T32A_COUNT_STOP ((uint32_t)0x0000004) 116 #define T32A_COUNT_DONT_START ((uint32_t)0x0000000) 117 #define T32A_COUNT_START ((uint32_t)0x0000002) 127 #define T32A_RUN_DISABLE ((uint32_t)0x00000000) 128 #define T32A_RUN_ENABLE ((uint32_t)0x00000001) 139 #define T32A_PRSCLx_1 ((uint32_t)0x00000000) 140 #define T32A_PRSCLx_2 ((uint32_t)0x10000000) 141 #define T32A_PRSCLx_8 ((uint32_t)0x20000000) 142 #define T32A_PRSCLx_32 ((uint32_t)0x30000000) 143 #define T32A_PRSCLx_128 ((uint32_t)0x40000000) 144 #define T32A_PRSCLx_256 ((uint32_t)0x50000000) 145 #define T32A_PRSCLx_512 ((uint32_t)0x60000000) 146 #define T32A_PRSCLx_1024 ((uint32_t)0x70000000) 156 #define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) 157 #define T32A_CLKx_INTRG ((uint32_t)0x01000000) 158 #define T32A_CLKx_TIM_RISING_EDGE ((uint32_t)0x02000000) 159 #define T32A_CLKx_TIM_TRAILING_EDGE ((uint32_t)0x03000000) 160 #define T32A_CLKx_EXTTRG_RISING_EDGE ((uint32_t)0x04000000) 161 #define T32A_CLKx_EXTTRG_TRAILING_EDGE ((uint32_t)0x05000000) 171 #define T32A_WBF_DISABLE ((uint32_t)0x00000000) 172 #define T32A_WBF_ENABLE ((uint32_t)0x00100000) 182 #define T32A_COUNT_UP ((uint32_t)0x00000000) 183 #define T32A_COUNT_DOWN ((uint32_t)0x00010000) 184 #define T32A_COUNT_UPDOWN ((uint32_t)0x00020000) 185 #define T32A_COUNT_PLS ((uint32_t)0x00030000) 195 #define T32A_RELOAD_NON ((uint32_t)0x00000000) 196 #define T32A_RELOAD_INTRG ((uint32_t)0x00000100) 197 #define T32A_RELOAD_EXTTRG_RISING_EDGE ((uint32_t)0x00000200) 198 #define T32A_RELOAD_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000300) 199 #define T32A_RELOAD_TIM_RISING_EDGE ((uint32_t)0x00000400) 200 #define T32A_RELOAD_TIM_TRAILING_EDGE ((uint32_t)0x00000500) 201 #define T32A_RELOAD_SYNC ((uint32_t)0x00000600) 202 #define T32A_RELOAD_TREGx ((uint32_t)0x00000700) 212 #define T32A_STOP_NON ((uint32_t)0x00000000) 213 #define T32A_STOP_INTRG ((uint32_t)0x00000010) 214 #define T32A_STOP_EXTTRG_RISING_EDGE ((uint32_t)0x00000020) 215 #define T32A_STOP_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000030) 216 #define T32A_STOP_TIM_RISING_EDGE ((uint32_t)0x00000040) 217 #define T32A_STOP_TIM_TRAILING_EDGE ((uint32_t)0x00000050) 218 #define T32A_STOP_SYNC ((uint32_t)0x00000060) 219 #define T32A_STOP_TREGx ((uint32_t)0x00000070) 230 #define T32A_START_NON ((uint32_t)0x00000000) 231 #define T32A_START_INTRG ((uint32_t)0x00000001) 232 #define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) 233 #define T32A_START_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000003) 234 #define T32A_START_TIM_RISING_EDGE ((uint32_t)0x00000004) 235 #define T32A_START_TIM_TRAILING_EDGE ((uint32_t)0x00000005) 236 #define T32A_START_SYNC ((uint32_t)0x00000006) 237 #define T32A_START_Rsvd ((uint32_t)0x00000007) 247 #define T32A_OCR_DISABLE ((uint32_t)0x00000000) 248 #define T32A_OCR_SET ((uint32_t)0x00000001) 249 #define T32A_OCR_CLR ((uint32_t)0x00000002) 250 #define T32A_OCR_INVERSION ((uint32_t)0x00000003) 260 #define T32A_OCRCAPx1_DISABLE ((uint32_t)0x00000000) 261 #define T32A_OCRCAPx1_SET ((uint32_t)0x00000040) 262 #define T32A_OCRCAPx1_CLR ((uint32_t)0x00000080) 263 #define T32A_OCRCAPx1_INVERSION ((uint32_t)0x000000C0) 273 #define T32A_OCRCAPx0_DISABLE ((uint32_t)0x00000000) 274 #define T32A_OCRCAPx0_SET ((uint32_t)0x00000010) 275 #define T32A_OCRCAPx0_CLR ((uint32_t)0x00000020) 276 #define T32A_OCRCAPx0_INVERSION ((uint32_t)0x00000030) 286 #define T32A_OCRCMPx1_DISABLE ((uint32_t)0x00000000) 287 #define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) 288 #define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) 289 #define T32A_OCRCMPx1_INVERSION ((uint32_t)0x0000000C) 299 #define T32A_OCRCMPx0_DISABLE ((uint32_t)0x00000000) 300 #define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) 301 #define T32A_OCRCMPx0_CLR ((uint32_t)0x00000002) 302 #define T32A_OCRCMPx0_INVERSION ((uint32_t)0x00000003) 312 #define T32A_RGx0_MASK ((uint32_t)0x0000FFFF) 313 #define T32A_RGC0_MASK ((uint32_t)0xFFFFFFFF) 323 #define T32A_RGx1_MASK ((uint32_t)0x0000FFFF) 324 #define T32A_RGC1_MASK ((uint32_t)0xFFFFFFFF) 334 #define T32A_TMRx_MASK ((uint32_t)0x0000FFFF) 335 #define T32A_TMRC_MASK ((uint32_t)0xFFFFFFFF) 345 #define T32A_RELDx_MASK ((uint32_t)0x0000FFFF) 346 #define T32A_RELDC_MASK ((uint32_t)0xFFFFFFFF) 356 #define T32A_CAPMx1_DISABLE ((uint32_t)0x00000000) 357 #define T32A_CAPMx1_INTRG ((uint32_t)0x00000010) 358 #define T32A_CAPMx1_INx0_RISING_EDGE ((uint32_t)0x00000020) 359 #define T32A_CAPMx1_INx0_TRAILING_EDGE ((uint32_t)0x00000030) 360 #define T32A_CAPMx1_INx1_RISING_EDGE ((uint32_t)0x00000040) 361 #define T32A_CAPMx1_INx1_TRAILING_EDGE ((uint32_t)0x00000050) 362 #define T32A_CAPMx1_TIM_RISING_EDGE ((uint32_t)0x00000060) 363 #define T32A_CAPMx1_TIM_TRAILING_EDGE ((uint32_t)0x00000070) 373 #define T32A_CAPMx0_DISABLE ((uint32_t)0x00000000) 374 #define T32A_CAPMx0_INTRG ((uint32_t)0x00000001) 375 #define T32A_CAPMx0_INx0_RISING_EDGE ((uint32_t)0x00000002) 376 #define T32A_CAPMx0_INx0_TRAILING_EDGE ((uint32_t)0x00000003) 377 #define T32A_CAPMx0_INx1_RISING_EDGE ((uint32_t)0x00000004) 378 #define T32A_CAPMx0_INx1_TRAILING_EDGE ((uint32_t)0x00000005) 379 #define T32A_CAPMx0_TIM_RISING_EDGE ((uint32_t)0x00000006) 380 #define T32A_CAPMx0_TIM_TRAILING_EDGE ((uint32_t)0x00000007) 390 #define T32A_CAPx0_MASK ((uint32_t)0x0000FFFF) 391 #define T32A_CAPC0_MASK ((uint32_t)0xFFFFFFFF) 401 #define T32A_CAPx1_MASK ((uint32_t)0x0000FFFF) 402 #define T32A_CAPC1_MASK ((uint32_t)0xFFFFFFFF) 412 #define T32A_IMSTERR_MASK_NOREQ ((uint32_t)0x00000000) 413 #define T32A_IMSTERR_MASK_REQ ((uint32_t)0x00000010) 423 #define T32A_IMUFx_MASK_NOREQ ((uint32_t)0x00000000) 424 #define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) 434 #define T32A_IMOFx_MASK_NOREQ ((uint32_t)0x00000000) 435 #define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) 445 #define T32A_IMx1_MASK_NOREQ ((uint32_t)0x00000000) 446 #define T32A_IMx1_MASK_REQ ((uint32_t)0x00000002) 456 #define T32A_IMx0_MASK_NOREQ ((uint32_t)0x00000000) 457 #define T32A_IMx0_MASK_REQ ((uint32_t)0x00000001) 467 #define T32A_INTSTERR_FLG_MASK ((uint32_t)0x00000010) 468 #define T32A_INTSTERR_FLG_CLR ((uint32_t)0x00000010) 478 #define T32A_INTUFx_FLG_MASK ((uint32_t)0x00000008) 479 #define T32A_INTUFx_FLG_CLR ((uint32_t)0x00000008) 489 #define T32A_INTOFx_FLG_MASK ((uint32_t)0x00000004) 490 #define T32A_INTOFx_FLG_CLR ((uint32_t)0x00000004) 500 #define T32A_INTx1_FLG_MASK ((uint32_t)0x00000002) 501 #define T32A_INTx1_FLG_CLR ((uint32_t)0x00000002) 511 #define T32A_INTx0_FLG_MASK ((uint32_t)0x00000001) 512 #define T32A_INTx0_FLG_CLR ((uint32_t)0x00000001) 522 #define T32A_DMAENx2_DISABLE ((uint32_t)0x00000000) 523 #define T32A_DMAENx2_ENABLE ((uint32_t)0x00000004) 533 #define T32A_DMAENx1_DISABLE ((uint32_t)0x00000000) 534 #define T32A_DMAENx1_ENABLE ((uint32_t)0x00000002) 544 #define T32A_DMAENx0_DISABLE ((uint32_t)0x00000000) 545 #define T32A_DMAENx0_ENABLE ((uint32_t)0x00000001) 555 #define T32A_PDN_NON0 ((uint32_t)0x00000000) 556 #define T32A_PDN_NON1 ((uint32_t)0x00001000) 557 #define T32A_PDN_INC0_RISING_EDGE ((uint32_t)0x00002000) 558 #define T32A_PDN_INC0_TRAILING_EDGE ((uint32_t)0x00003000) 559 #define T32A_PDN_INC1_RISING_EDGE ((uint32_t)0x00004000) 560 #define T32A_PDN_INC1_TRAILING_EDGE ((uint32_t)0x00005000) 561 #define T32A_PDN_INC0_BOTH_EDGE ((uint32_t)0x00006000) 562 #define T32A_PDN_INC1_BOTH_EDGE ((uint32_t)0x00007000) 572 #define T32A_PUP_NON0 ((uint32_t)0x00000000) 573 #define T32A_PUP_NON1 ((uint32_t)0x00000100) 574 #define T32A_PUP_INC0_RISING_EDGE ((uint32_t)0x00000200) 575 #define T32A_PUP_INC0_TRAILING_EDGE ((uint32_t)0x00000300) 576 #define T32A_PUP_INC1_RISING_EDGE ((uint32_t)0x00000400) 577 #define T32A_PUP_INC1_TRAILING_EDGE ((uint32_t)0x00000500) 578 #define T32A_PUP_INC0_BOTH_EDGE ((uint32_t)0x00000600) 579 #define T32A_PUP_INC1_BOTH_EDGE ((uint32_t)0x00000700) 589 #define T32A_NF_NON ((uint32_t)0x00000000) 590 #define T32A_NF_2 ((uint32_t)0x00000010) 591 #define T32A_NF_4 ((uint32_t)0x00000020) 592 #define T32A_NF_8 ((uint32_t)0x00000030) 602 #define T32A_PDIR_FORWARD ((uint32_t)0x00000000) 603 #define T32A_PDIR_BACKWARD ((uint32_t)0x00000002) 613 #define T32A_PMODE_PHASE_2 ((uint32_t)0x00000000) 614 #define T32A_PMODE_PHASE_1 ((uint32_t)0x00000001) 958 void (*handler_T)(uint32_t id, uint32_t status, TXZ_Result result);
959 void (*handler_TC0)(uint32_t id, uint32_t status, TXZ_Result result);
960 void (*handler_TC1)(uint32_t id, uint32_t status, TXZ_Result result);
1008 TXZ_Result
t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl);
t32_regnum_t
Use of Timer register number.
Definition: txz_t32a.h:646
T32A Counter Capture Register A Setting structure definenition.
Definition: txz_t32a.h:818
t32a_outcrx0_t outcrx0
Definition: txz_t32a.h:946
t32a_capx0_t capx0
Definition: txz_t32a.h:953
uint32_t ocrcap1
Definition: txz_t32a.h:764
t32a_rgx0_t rgx0
Definition: txz_t32a.h:949
Definition: txz_t32a.h:674
Definition: txz_t32a.h:648
Capture Control Setting structure definenition.
Definition: txz_t32a.h:780
TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type)
Timer Start in interrupt mode.
Definition: txz_t32a.c:1442
t32a_mode_t mode
Definition: txz_t32a.h:970
uint32_t imof
Definition: txz_t32a.h:872
Status register structure definenition.
Definition: txz_t32a.h:886
T32A Counter Reload Register Setting structure definenition.
Definition: txz_t32a.h:830
Definition: txz_t32a.h:675
uint32_t mode
Definition: txz_t32a.h:698
T32A Capture Register x0 Setting structure definenition.
Definition: txz_t32a.h:854
uint32_t imsterr
Definition: txz_t32a.h:868
T32A Capture Register x0 Setting structure definenition.
Definition: txz_t32a.h:842
Definition: txz_t32a.h:671
uint32_t intuf
Definition: txz_t32a.h:890
uint32_t pdir
Definition: txz_t32a.h:930
t32_type_t
Use of Timer register.
Definition: txz_t32a.h:634
Pulse Count Control register setting structure definenition.
Definition: txz_t32a.h:922
TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val)
Timer Register Value Read.
Definition: txz_t32a.c:1695
TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type)
Timer Stop in interrupt mode.
Definition: txz_t32a.c:1601
t32a_initial_setting_t init[T32A_TIMERMAX]
Definition: txz_t32a.h:983
uint32_t run
Definition: txz_t32a.h:716
uint32_t ocrcmp0
Definition: txz_t32a.h:770
uint32_t pup
Definition: txz_t32a.h:926
Initial Timer setting structure definenition.
Definition: txz_t32a.h:941
T32A Timer Register x1 Setting structure definenition.
Definition: txz_t32a.h:806
uint32_t stop
Definition: txz_t32a.h:738
t32a_runx_t runx
Definition: txz_t32a.h:944
Definition: txz_t32a.h:650
uint32_t dmaenx2
Definition: txz_t32a.h:908
TimerA Mode Setting structure definenition.
Definition: txz_t32a.h:694
TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type)
Timer Start in interrupt mode.
Definition: txz_t32a.c:1543
uint32_t capx0
Definition: txz_t32a.h:844
uint32_t id
Definition: txz_t32a.h:943
T32A Timer Register x0 Setting structure definenition.
Definition: txz_t32a.h:794
TSB_T32A_TypeDef * p_instance
Definition: txz_t32a.h:981
uint32_t capmx1
Definition: txz_t32a.h:782
uint32_t ocr
Definition: txz_t32a.h:752
TXZ_Result t32a_mode_init(t32a_t *p_obj)
Mode Initialize the T32A object.
Definition: txz_t32a.c:1163
uint32_t rgx1
Definition: txz_t32a.h:808
t32_mode_t
Use of Timer register.
Definition: txz_t32a.h:656
Definition: txz_t32a.h:672
Initial Mode setting structure definenition.
Definition: txz_t32a.h:968
uint32_t runflg
Definition: txz_t32a.h:710
t32a_capx1_t capx1
Definition: txz_t32a.h:954
uint32_t capx1
Definition: txz_t32a.h:856
uint32_t imuf
Definition: txz_t32a.h:870
TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type)
Get status.
Definition: txz_t32a.c:1739
Definition: txz_t32a.h:659
t32a_imx_t imx
Definition: txz_t32a.h:955
uint32_t intsterr
Definition: txz_t32a.h:888
t32a_pulse_cr_t pls_cr
Definition: txz_t32a.h:957
uint32_t dmaenx1
Definition: txz_t32a.h:910
uint32_t imx1
Definition: txz_t32a.h:874
Definition: txz_t32a.h:662
TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type)
Timer Stop in interrupt mode.
Definition: txz_t32a.c:1500
struct t32a_handle t32a_t
T32A handle structure definenition.
Counter Register Control Setting structure definenition.
Definition: txz_t32a.h:726
Definition: txz_t32a.h:638
uint32_t rgx0
Definition: txz_t32a.h:796
TimerA Run Control Setting structure definenition.
Definition: txz_t32a.h:708
t32a_reldx_t reldx
Definition: txz_t32a.h:952
uint32_t clk
Definition: txz_t32a.h:730
All common macro and definition for TXZ peripheral drivers.
TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl)
Calculate timer value to set timer register.
Definition: txz_t32a.c:1952
Definition: txz_t32a.h:649
uint32_t prscl
Definition: txz_t32a.h:728
Definition: txz_t32a.h:637
t32a_dma_req_t dma_req
Definition: txz_t32a.h:956
T32A handle structure definenition.
Definition: txz_t32a.h:979
T32AxOUTA Control Setting structure definenition.
Definition: txz_t32a.h:762
uint32_t nf
Definition: txz_t32a.h:928
TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value)
Timer Register Value Setting.
Definition: txz_t32a.c:1646
uint32_t dmaenx0
Definition: txz_t32a.h:912
TimerA Output Control Setting structure definenition.
Definition: txz_t32a.h:750
Definition: txz_t32a.h:673
uint32_t sftstp
Definition: txz_t32a.h:712
Interrupt mask register Setting structure definenition.
Definition: txz_t32a.h:866
uint32_t halt
Definition: txz_t32a.h:696
DMA Request register setting structure definenition.
Definition: txz_t32a.h:906
t32a_rgx1_t rgx1
Definition: txz_t32a.h:950
t32a_tmrx_t tmrx
Definition: txz_t32a.h:951
uint32_t updn
Definition: txz_t32a.h:734
uint32_t pmode
Definition: txz_t32a.h:932
uint32_t ocrcmp1
Definition: txz_t32a.h:768
t32a_capcrx_t capcrx
Definition: txz_t32a.h:948
uint32_t imx0
Definition: txz_t32a.h:876
uint32_t ocrcap0
Definition: txz_t32a.h:766
t32a_initial_mode_t init_mode
Definition: txz_t32a.h:982
TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type)
Initialize the T32A object.
Definition: txz_t32a.c:1193
uint32_t intx0
Definition: txz_t32a.h:896
void t32a_timer_cap0_IRQHandler(t32a_t *p_obj)
IRQ Timer Capture0 Handler for Timer Capture0 interrupt.
Definition: txz_t32a.c:1845
t32_triger_t
Use of Timer register.
Definition: txz_t32a.h:669
uint32_t wbf
Definition: txz_t32a.h:732
uint32_t capmx0
Definition: txz_t32a.h:784
TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type)
Release the T32A object.
Definition: txz_t32a.c:1395
Definition: txz_t32a.h:660
uint32_t tmrx
Definition: txz_t32a.h:820
t32a_outcrx1_t outcrx1
Definition: txz_t32a.h:947
uint32_t reld
Definition: txz_t32a.h:736
Definition: txz_t32a.h:661
uint32_t start
Definition: txz_t32a.h:740
uint32_t pdn
Definition: txz_t32a.h:924
uint32_t sftsta
Definition: txz_t32a.h:714
void t32a_timer_IRQHandler(t32a_t *p_obj)
IRQ Handler for Timer interrupt.
Definition: txz_t32a.c:1790
Definition: txz_t32a.h:658
uint32_t intof
Definition: txz_t32a.h:892
Definition: txz_t32a.h:636
void t32a_timer_cap1_IRQHandler(t32a_t *p_obj)
IRQ Timer Capture1 Handler for Timer Capture1 interrupt.
Definition: txz_t32a.c:1900
uint32_t reld
Definition: txz_t32a.h:832
uint32_t intx1
Definition: txz_t32a.h:894
t32a_crx_t crx
Definition: txz_t32a.h:945