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Toshiba Announces Immediate Availability of IP Subsystem for Implementing 10 Gigabit Ethernet on Custom LSI Platforms

23rd March 2016

Toshiba Semiconductor & Storage Products Company announced today the immediate availability of an IP subsystem that has been developed in conjunction with MoreThanIP, a provider of leading edge telecom solutions. The solution is designed to easily implement a 10 Gigabit Ethernet interface subsystem into a system LSI.

The IP subsystem consists of a 10 Gigabit Ethernet MAC (media access controller), PCS (physical coding sublayer) and high-speed SerDes (Serializer Deserializer) for custom LSI platforms, including ASIC and Toshiba’s FFSATM.

The subsystem implements a 4-lane XAUI or a single Lane XFI interface that provides connectivity to a large number of Ethernet PHYs and controller ASSPs (Application Specific Standard Products). With support for PFC (Priority Flow Control) and a high level of flexibility, the IP subsystem is particularly suited for data centres and telecoms applications.

"Together with Toshiba custom LSI solutions and MoreThanIP proven cores, chip producers will now have an integrated solution at their disposal to help speed the design cycle and meet the needs of the growing high-speed Ethernet market," said Francois Balay, CEO of MoreThanIP.

"Collaboration with MoreThanIP allows us to propose an integrated Ethernet offering with best-in-class IP cores for custom LSI solutions," said Yukihiro Urakawa, Technical Executive of Toshiba.

Toshiba leverages comprehensive expertise from design to manufacture to offer a wide range of custom LSI solutions. FFSA is a new, flexible custom LSI solution with pre-designed masters featuring configurable I/Os, SerDes, SRAMs and logic devices that can be configured according to customer requirements.

Going forward, Toshiba will continue to provide solutions that help customers to optimize their system design and achieve timely product development.

* FFSA is a trademark of Toshiba Corporation. FFSA technology enables Toshiba to develop integrated circuits with much lower development costs and much shorter development turn-around times by reducing the number of metal layers that must be customized.

Ethernet Terminology

MAC: Data transfer control technology such as frame synchronization, flow control and error checking
PCS: Physical protocol layer that encodes data for high-speed Ethernet, Gigabit Ethernet and 10 Gigabit Ethernet
SerDes: A pair of functional blocks that convert data between serial data and parallel interfaces in each direction for high speed communications.
XAUI: Electrical interface for 10 Gigabit Ethernet to communicate via a 4-lane serial line.
XFI: Electrical interface for 10 Gigabit Ethernet to communicate via a 1-lane serial line.
PFC: Technology defined in IEEE 802.1Qbb for lossless Ethernet communication with priority flow control for each data.

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