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My FPGA engineers are working on other projects now, can I give you my RTL and timing constraints and receive an equivalent device back? What do I need to prepare?

Yes, Toshiba needs clean RTL and timing constraints SDC file. In addition to that, we will also need to know the existing package pin-out information so that we can provide with the same footprint solution as an existing FPGA.

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·Before creating and producing designs and using, customers must also refer to and comply with the latest versions of all relevant TOSHIBA information and the instructions for the application that Product will be used with or for.