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Combatting Heat Dissipation Issues as Higher Density Power Systems are Deployed

Rapidly escalating power densities in semiconductor devices are being expected in order to provide consumers with sleeker, more attractive electronic products that possess greater functionality while also supporting longer periods between recharges. As a result, the specification of key elements of the power system, such as MOSFETs, must be given substantial consideration, so that well-reasoned procurement decisions are made. As higher power density devices are employed, the issue of coping with the increased generation of heat energy needs to be tackled. This means that effective thermal management now, more than ever, is vital to modern power system design - and this should clearly start at the component level.

Combatting Heat Dissipation Issues as Higher Density Power Systems are Deployed

The cooling mechanisms generally used in electronics hardware to dissipate heat energy (heatsinks, fans, heatpipes, etc.) add significantly to the cost, size and complexity of the system. These are all things that engineers want to avoid as much as possible, as they have to deal with an array of different constraints - in terms of available board space, time to market and the unit cost of the end product. Moving to higher power densities achieves absolutely nothing if the disadvantages end up outweighing the benefits. Cooling fans, it should be noted, prove particularly inconvenient, as not only do they expand the size of the enclosure needed, they also contribute to the system’s power budget. Furthermore, inclusion of fans prevents sealing of the enclosure (leaving the electronics inside potentially exposed to dust or moisture ingress) and, as they have moving parts involved, operational failures can occur.
 

Engineers simply cannot afford to ignore the heat dissipation issue, but a new approached is needed. They have always had the unenviable task of balancing power efficiency characteristics and switching speeds. By minimising the MOSFET’s gate charge (Qg) it has been possible to achieve higher switching speeds, but this has meant greater power losses - as the on-state resistance (RDS(ON)) has risen. In contrast efforts to curb the RDS(ON) to mitigate power losses have led to poorer switching performance being witnessed. It isn’t possible, with any given device, to make enhancements to one of these parameters without having the other one suffer to some degree. This is why MOSFET datasheets will normally reference both these parameters together in the form of the following figure of merit:
 

RDS(ON) x Qg
 

Unable to break this loop, engineers need ground-breaking innovation from power IC manufacturers, so that better MOSFET figure of merits are forthcoming. The introduction of new generations of semiconductor process technologies, along with the implementation of better realised trench arrangements, are set to enable power conversion efficiencies to be boosted. This means that the desired improvements to MOSFET figure of merit values can be brought about. At the same time significant advances in power IC packaging design are taking place. Over the years traditional package formats have been supplanted - first through-hole gave way to ball grid arrays, now thermal pads are being replaced by copper clips. The subsequent thermal conductivity improvements are enabling the heat energy generated to be removed from devices in a much more effective manner (carrying heat away from both the topside and the underside of the die).

To find out more about Toshiba’s latest innovations in MOSFET design and how these are facilitating systems with higher power densities, download the following white paper:

Click here to learn more about Toshiba's innovations in power IC design

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