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Mid-volume custom SoCs without ASICs or FPGAs

Mid-volume custom SoCs without ASICs or FPGAs

An ever-growing number of applications require a custom system-on-chip (SoC) to address design requirements that cannot be met using standard off-the-shelf semiconductors. Engineers are faced with a challenge, though, as the two established methods for developing custom SoCs - namely application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs) - both have drawbacks. This is especially true when the volumes involved are somewhere in the mid-range.
 

ASICs offer the benefits of a fully custom solution - with low unit costs, very high computational performance and minimal power consumption. However, this is only really applicable where volumes are large enough to cover sizeable initial financial investment non-recurring engineering (NRE) costs. In addition, development can take several months and a ‘hardwired’ approach offers no flexibility for alteration. If new functionality needs to be added (or a bug in the hardware removed) an expensive ASIC re-spin will be required.
 

Conversely, programmable logic offers advantages of flexibility and low upfront costs. FPGAs can be implemented far quicker than their ASIC counterparts and require less engineering resources. This must be balanced against the higher unit price tags, higher power consumption and relatively lower performance.
 

Both options are a commercial gamble. If the ASIC-based solution doesn’t realise expected sales volumes then the investment may be difficult to recover. However, if shipments of a programmable logic solution are higher than predicted, the unit cost of the FPGAs may result in lower profit margins than could have been possible.
 

One alternative to both FPGAs and ASICs is Toshiba’s Fit-Fast Structured Array (FFSATM) technology. FFSA allows engineers to mitigate risk by supporting the development of high-performance, low-power custom SoCs at reasonable unit costs. This means that they are optimised for the mid-volume market.

TCM0345_FFSA

FFSA devices utilise a wide breadth of IP that encompasses logic, memory, connectivity and mixed-signal elements. Devices can be built with up to 46 million logic gates and processing speeds reaching 1000 MHz. They can embed 88 Mbits of SRAM memory capacity and up to 40 channels of high-speed connectivity (supporting 28 Gbps data rates). The next generation of arrays, which are now under development, will push the performance envelope still further.

FFSA technology is based on the fact that only interconnects need to be customised to access the key elements needed for a particular design. This means that just a few metal layers are called for. As a consequence, development cycles, compared to a typical ASIC, can be shortened from three months to less than six weeks. Overall costs can be reduced by as much as 65%.

Download our comprehensive whitepaper to learn more about Toshiba’s FFSATM technology.

Click here to find out more about 'A Custom SoC Design Alternative to ASIC and FPGA'

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·Before creating and producing designs and using, customers must also refer to and comply with the latest versions of all relevant TOSHIBA information and the instructions for the application that Product will be used with or for.