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Restriction for Using the /BUSRQ Signal

Product name
TOSHIBA Microcontrollers TX19 Family TX19 Series
  • TMP1942CYU
  • TMP1942CZU
  • TMP1942FDU
  • TMP1942CZXB
  • TMP1942FDXB

Dear Customer

With regard to the TX19 Family microcontrollers listed above, please be advised that the external bus interface logic may not insert the specified number of wait states if the /BUSRQ signal is asserted, as described below.

If the /BUSRQ signal is asserted when the <ALESEL> bit in the SYSCR3 register is set to “1” (long) and automatic wait-state generation is enabled for external bus accesses, the external bus interface logic may not insert wait states one state less than the specified number.
Counter Measure
Please avoid the above problem by programming as explained below.
When the SYSCR3<ALESEL> bit is set to “1” (long) and the /BUSRQ signal is used for external bus accesses, the number of wait states should be set to one state longer than the desired period.


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