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Restriction use of Interrupt Controller

Product name
TOSHIBA Microcontrollers 900 Family
  • TMP92CH21
  • TMP92CA25

Dear Customer

Regarding the products shown below, Toshiba have found they may experience the problem with interrupt controller if they use it under certain conditions.

Problem
INTTC: end interruption of micro DMA, may not occur even micro DMA transmission was completed.
Condition
  • Condition1: the read cycle of external memory with 1-wait or more setting
  • Condition2: SDRAM is used
  • Condition3: BUSREQ function is used (an external BUSREQ and internal LCD controller)

If interrupt for starting Micro DMA is asserted at the same time as the specific instruction of CPU in any of the three above-mentioned conditions, a problem may occur.

Workaround
Software solution for this restriction.
To avoid the problem, set "1" at 7th bit of the "SIMC" register.
(The current datasheet describes that "0" should be set at this bit.)
If you don't use micro DMA end interruption, you don't need to set "1" at 7th bit of the "SIMC" register.

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·Before creating and producing designs and using, customers must also refer to and comply with the latest versions of all relevant TOSHIBA information and the instructions for the application that Product will be used with or for.