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About information presented in this cross reference

The information presented in this cross reference is based on TOSHIBA's selection criteria and should be treated as a suggestion only. Please carefully review the latest versions of all relevant information on the TOSHIBA products, including without limitation data sheets and validate all operating parameters of the TOSHIBA products to ensure that the suggested TOSHIBA products are truly compatible with your design and application.
Please note that this cross reference is based on TOSHIBA's estimate of compatibility with other manufacturers' products, based on other manufacturers' published data, at the time the data was collected.
TOSHIBA is not responsible for any incorrect or incomplete information. Information is subject to change at any time without notice.

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My FPGA engineers are working on other projects now, can I give you my RTL and timing constraints and receive an equivalent device back? What do I need to prepare?

Yes, Toshiba needs clean RTL and timing constraints SDC file. In addition to that, we will also need to know the existing package pin-out information so that we can provide with the same footprint solution as an existing FPGA.

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