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Subsystems

Toshiba provides the CPU, interface and memory subsystems necessary for SoC development.
The use of these subsystems allows you to dedicate your design resources to the development of differentiating features that is primary objective to develop a custom SoC.

CPU Subsystems

Readily Available CPU-Related Features
  • Pre-verified hardware and software
  • ARM® cores (CM4/CR4/CA53), DMAC, SRAM, peripheral IP cores
  • Extended bus interfaces for user logic
  • Support for Easy Prototyping

CPU Subsystems

ARM® Cortex®-Based CPU Subsystems
SS_CPU_M4 SS_CPU_R4 SS_CPU_A53
CPU CPU Cortex-M4F Cortex-R4 Cortex-A53
# of cores 1 1 1
L1 cache/core - I32KB D32KB I32KB D32KB
TCM/core - I32KB D32KB
(configurable)
-
L2 cache - - 256KB
Interrupt controller NVIC VIC GIC
Bus IF master AHB 32b x3 AXI 64b x1 AXI 128b x1
Bus IF slave
(inc. intr ctrl.)
- AHB 32b x1
AXI 64b x1
AXI 32b x1
SRAM on bus Configurable up to 2MB
DMAC ARM DMA330 8ch
Timer x10
UART x2
I2C Master x2 (Standard/Fast/Fast+), Slave x1
SPI flash memory IF Single/Dual/Quad CS x2
SPI device controller Master x2 Slave x1
GPIO x64
Extension bus IF Outbound AXI 128b x2, APB 32b x1
Inbound AXI 128b x1

IP Subsystems

Subsystems that integrate essential functions for high-speed interfacing
  • Pre-verified by Toshiba and IP vendors
  • Optional offering of control software
  • Usable with a PHY on FPGA, ASIC and FFSA™ platforms without RTL modification
    ・Selection of FPGA-proven controller IP cores enables Easy Prototyping

IP Subsystems

*FFSA is a trademark of Toshiba Corporation.

*ARM and Cortex are registered trademarks of ARM Limited (or its subsidiary) in the EU and countries elsewhere.

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·Before creating and producing designs and using, customers must also refer to and comply with the latest versions of all relevant TOSHIBA information and the instructions for the application that Product will be used with or for.