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Subsystems (子系統)

東芝提供SoC開發所需的CPU,介面和memory 內存子系統。這些子系統的使用使您可以將您的設計資源用於開發差異化功能,這是開發客制化SoC的主要目標。

CPU 子系統

隨時可用的CPU相關功能
  • 預先驗證的硬體及軟體
  • ARM® cores (CM4/CR4/CA53), DMAC, SRAM, peripheral IP cores
  • 為User logic擴展bus interfaces
  • 支援 Easy Prototyping

CPU Subsystems

ARM® Cortex®-Based CPU Subsystems
SS_CPU_M4 SS_CPU_R4 SS_CPU_A53
CPU CPU Cortex-M4F Cortex-R4 Cortex-A53
# of cores 1 1 1
L1 cache/core - I32KB D32KB I32KB D32KB
TCM/core - I32KB D32KB
(configurable)
-
L2 cache - - 256KB
Interrupt controller NVIC VIC GIC
Bus IF master AHB 32b x3 AXI 64b x1 AXI 128b x1
Bus IF slave
(inc. intr ctrl.)
- AHB 32b x1
AXI 64b x1
AXI 32b x1
SRAM on bus Configurable up to 2MB
DMAC ARM DMA330 8ch
Timer x10
UART x2
I2C Master x2 (Standard/Fast/Fast+), Slave x1
SPI flash memory IF Single/Dual/Quad CS x2
SPI device controller Master x2 Slave x1
GPIO x64
Extension bus IF Outbound AXI 128b x2, APB 32b x1
Inbound AXI 128b x1

IP 子系統

Subsystems that integrate essential functions for high-speed interfacing
  • P經過東芝和IP供應商的預先驗證
  • 提供選擇性軟體
  • 可在FPGA,ASIC和FFSA™平台上使用PHY,無需修改RTL
    ・選擇經FPGA驗證的控制 IP cores 可以實現 Easy Prototyping

IP Subsystems

*ARM and Cortex are registered trademarks of ARM Limited (or its subsidiary) in the EU and countries elsewhere.

* All other company names, product names, and service names mentioned herein may be trademarks of their respective companies.

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