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The information presented in this cross reference is based on TOSHIBA's selection criteria and should be treated as a suggestion only. Please carefully review the latest versions of all relevant information on the TOSHIBA products, including without limitation data sheets and validate all operating parameters of the TOSHIBA products to ensure that the suggested TOSHIBA products are truly compatible with your design and application.
Please note that this cross reference is based on TOSHIBA's estimate of compatibility with other manufacturers' products, based on other manufacturers' published data, at the time the data was collected.
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Operation or stop processing of each function

Each function block can be operated or stopped by the following list of the register setting.

Function Unit / Channel Register Register function Value A Value B Initial value
DMA A DMAAStatus<master_enable> DMA operation 0:Disabled 1:Enabled 0:Disabled
DMAACfg<master_enable> DMA operation 0:Disabled 1:Enabled 0:Disabled
B DMABStatus<master_enable> DMA operation 0:Disabled 1:Enabled 0:Disabled
DMABCfg<master_enable> DMA operation 0:Disabled 1:Enabled 0:Disabled
ADC A/B CGSYSCR<FCSTOP> ADC clock 0:Active 1:Stop 0:Active
A ADAMOD1<DACON> Circuit ON/OFF control 0:OFF 1:ON 0:OFF
ADAMOD1<I2AD> ADC operation control in IDLE mode 0:Stop 1:Operate 0:Stop
ADAMOD1<RCUT> Reference current 0:During conversion 1:Always 0:During conversion
B ADBMOD1<DACON> Circuit ON/OFF control 0:OFF 1:ON 0:OFF
ADBMOD1<I2AD> ADC operation control in IDLE mode 0:Stop 1:Operate 0:Stop
ADBMOD1<RCUT> Reference current 0:During conversion 1:Always 0:During conversion
DAC 0 DACCNT0<VREFON> VREF control 0:VREF off 1:VREF on 0:VREF off
DACCNT0<OP> DAC operation 0:Stop 1:Operation 0:Stop
1 DACCNT1<VREFON> VREF control 0:VREF off 1:VREF on 0:VREF off
DACCNT1<OP> DAC operation 0:Stop 1:Operation 0:Stop
USB Host   CGCKSTP<USBHSTP> USBH clock control 0:operation 1:clock stop 0:operation
USB Device   CGCKSTP<USBDSTP> USBD clock control 0:operation 1:clock stop 0:operation
EtherMAC   CGCKSTP<ETHSTP> EtherMac clock control 0:operation 1:clock stop 0:operation
CAN   CGCKSTP<CANSTP> CAN clock control 0:operation 1:clock stop 0:operation
SSP 0 SSP0CR1<SSE> SSP enable/disable 0:Disable 1:Enable 0:Disable
1 SSP1CR1<SSE> SSP enable/disable 0:Disable 1:Enable 0:Disable
2 SSP2CR1<SSE> SSP enable/disable 0:Disable 1:Enable 0:Disable
SIO/UART 0 SC0EN<SIOE> SIO/UART operation 0:disable 1:Operation 0:disable
1 SC1EN<SIOE> SIO/UART operation 0:disable 1:Operation 0:disable
2 SC2EN<SIOE> SIO/UART operation 0:disable 1:Operation 0:disable
3 SC3EN<SIOE> SIO/UART operation 0:disable 1:Operation 0:disable
UART 4 UART4CR<UARTEN> UART enable 0:Disable 1:Enable 0:Disable
5 UART5CR<UARTEN> UART enable 0:Disable 1:Enable 0:Disable
I2C/SIO 0 SBI0CR0<SBIEN> Serial bus interface operation 0:Disable 1:Enable 0:Disable
1 SBI1CR0<SBIEN> Serial bus interface operation 0:Disable 1:Enable 0:Disable
2 SBI2CR0<SBIEN> Serial bus interface operation 0:Disable 1:Enable 0:Disable
WDT   WDMOD<WDTE> Enable/Disable control 0:Disable 1:Enable 1:Enable
WDMOD<I2WDT> Operation when IDLE mode 0:Stop 1:In operation 0:Stop
TMRB 0 TB0EN<TBEN> TMRB0 operation 0:Disable 1:Enable 0:Disable
TB0CR<I2TB> Operation at IDLE mode 0:Stop 1:Operation 0:Stop
1 TB1EN<TBEN> TMRB1 operation 0:Disable 1:Enable 0:Disable
TB1CR<I2TB> Operation at IDLE mode 0:Stop 1:Operation 0:Stop
2 TB2EN<TBEN> TMRB2 operation 0:Disable 1:Enable 0:Disable
TB2CR<I2TB> Operation at IDLE mode 0:Stop 1:Operation 0:Stop
3 TB3EN<TBEN> TMRB3 operation 0:Disable 1:Enable 0:Disable
TB3CR<I2TB> Operation at IDLE mode 0:Stop 1:Operation 0:Stop
4 TB4EN<TBEN> TMRB4 operation 0:Disable 1:Enable 0:Disable
TB4CR<I2TB> Operation at IDLE mode 0:Stop 1:Operation 0:Stop
5 TB5EN<TBEN> TMRB5 operation 0:Disable 1:Enable 0:Disable
TB5CR<I2TB> Operation at IDLE mode 0:Stop 1:Operation 0:Stop
6 TB6EN<TBEN> TMRB6 operation 0:Disable 1:Enable 0:Disable
TB6CR<I2TB> Operation at IDLE mode 0:Stop 1:Operation 0:Stop
7 TB7EN<TBEN> TMRB7 operation 0:Disable 1:Enable 0:Disable
TB7CR<I2TB> Operation at IDLE mode 0:Stop 1:Operation 0:Stop
MPT 0 MT0EN<MTEN> MPT operation 0:Disable 1:Enable 0:Disable
MT0TBCR<MTI2TB> Controls clock operation to star/stop in IDLE mode 0:Stop 1:Start 0:Stop
1 MT1EN<MTEN> MPT operation 0:Disable 1:Enable 0:Disable
MT1TBCR<MTI2TB> Controls clock operation to star/stop in IDLE mode 0:Stop 1:Start 0:Stop
2 MT2EN<MTEN> MPT operation 0:Disable 1:Enable 0:Disable
MT2TBCR<MTI2TB> Controls clock operation to star/stop in IDLE mode 0:Stop 1:Start 0:Stop
3 MT3EN<MTEN> MPT operation 0:Disable 1:Enable 0:Disable
MT3TBCR<MTI2TB> Controls clock operation to star/stop in IDLE mode 0:Stop 1:Start 0:Stop
ENC 0 EN0TNCR<ENRUN> Encoder operation enable 0:Disable 1:Enable 0:Disable
1 EN1TNCR<ENRUN> Encoder operation enable 0:Disable 1:Enable 0:Disable
RMC   RMCEN<RMCEN> RMC operation 0:Disabled 1:Enabled 0:Disabled
RTC   RTCPAGER<ENATMR> Clock 0:Disable 1:Enable Undefined
LVD   LVDRCR<LVDEN1> Low voltage detection operation 0:Disabled 1:Enabled 1:Disabled
LVDICR<LVDEN2> Low voltage detection operation 0:Disabled 1:Enabled 0:Disabled
OFD   OFDCR2<OFDEN> Controls frequency detecting 0x00: Disable 0xE4: Enable 0x00: Disable
PLL   CGOSCCR<PLLON> PLL operation 0:Stop 1:Oscillation 0:Stop
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