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The information presented in this cross reference is based on TOSHIBA's selection criteria and should be treated as a suggestion only. Please carefully review the latest versions of all relevant information on the TOSHIBA products, including without limitation data sheets and validate all operating parameters of the TOSHIBA products to ensure that the suggested TOSHIBA products are truly compatible with your design and application.
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Function explanation : [Function explanation]

Simulation : [Clock frequency] [SPI format] [SSI format] [Microwire format]

Communication speed in the master mode (serial clock frequency)

Calculates the communication speed (serial clock frequency) when the synchronous serial interface is used in master mode. 
Communication speed is calculated according to system clock setting and serial channel setting.


Setting of system clock

High-speed clock(fc) fc MHz
fgear output fc  fc/2  fc/4  fc/8  fc/16 fgear(fsys) MHz

Setting of serial channel

TermSettingRange of input
Clock prescale divisor SSPxCPSR<CPSDVSR> Set an even number from 2 to 254.
Serial clock rate setting SSPxCR0<SCR> 0 to 255

Calculating formula of communication speed : Bit rate = fsys/(CPSDVSR*(1+SCR))


Communication speed (serial clock frequency)

The maximum communication speed available for the channel 0/1 is 10 Mbps and that for the channel 2 is 20 Mbps.
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