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The information presented in this cross reference is based on TOSHIBA's selection criteria and should be treated as a suggestion only. Please carefully review the latest versions of all relevant information on the TOSHIBA products, including without limitation data sheets and validate all operating parameters of the TOSHIBA products to ensure that the suggested TOSHIBA products are truly compatible with your design and application.
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Function explanation : [Function explanation]

Simulation : [Clock cycle] [Timer interrupt] [PPG output]

The source clock cycle of 16-bit timer and event counter and timer setting value are shown.

Setting method

  • Setting of system clock 
    The frequency of ΦT0 is determined in the system clock setting part.
  • Clock selection of the timer 
    Select clock output from prescaler in the timer.
  • Timer setting value 
    Input a numerical value to the preferred setting value, and select the unit. Clicking the calculation button will show you a timer setting value in the selected timer clock cycle.

Setting of system clock

High-speed clock(fc) fc MHz
fgear output fc  fc/2  fc/4  fc/8  fc/16 fgear MHz
fperiph output fc  fgear fperiph MHz
ΦT0 output fperiph  fperiph/2  fperiph/4  fperiph/8
fperiph/16  fperiph/32


Clock selection of the timer

<<Clock distribution diagram>>
SelectTBxMOD<TBCLK>Clock period
ΦT1 001 µs
ΦT4 010 µs
ΦT16 011 µs
ΦT32 100 µs
ΦT64 101 µs
ΦT128 110 µs
ΦT256 111 µs
A setting whose clock cycle is displayed as "-" cannot be used (because timer clock frequency < fsys is not filled).


Timer setting value

Preferred setting timeTimer setting value
uS mS S
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