New Technology from Toshiba Electronic Devices & Storage Corporation and Japan Semiconductor Corporation Enhances Reliability of N-channel LDMOS for 0.13-micron Generation Analog Power ICs

TOKYO and OITA--Toshiba Electronic Devices & Storage Corporation (“Toshiba”) and its manufacturing subsidiary, Japan Semiconductor Corporation, have enhanced the reliability of N-channel LDMOS ^[1] for 0.13-micron generation analog power ICs with a technology that suppresses time degradation of LDMOS caused by hot-carrier injection ^[2]. The technology boosts the lifetime of LDMOS over fivefold, and significantly improves the lifetime of analog power ICs ^[3].

Details of this achievement were reported on May 16 at the International Symposium on Power Semiconductor Devices and ICs 2018 (ISPSD 2018) in Chicago, an IEEE-sponsored international conference on power semiconductors.

Continued penetration of the Internet of Things and electric vehicles requires low voltage analog power ICs. In addition, ICs for automotive and industrial use must maintain high reliability, because vehicles and industrial machinery have long time operating. N-channel LDMOS, now being developed by many semiconductor companies, offers low Ron characteristics and high reliability, and is expected to work in motor control ICs and power management ICs.

However, Toshiba’s research work has found that N-channel LDMOS has a negative characteristic—a drastic increases in Off-state leakage current (“Ioff”) as a result of long-term use ^[4]. Increased Ioff causes circuit operation failure and increases stand-by power consumption. A solution that suppresses Ioff is essential for further promotion of N-channel LDMOS.

Using TCAD simulation and experiment data, Toshiba and Japan Semiconductor analyzed the Ioff mechanism, and identified two structures with the excellent tolerance required to overcome Ioff increases: a structure with extended STI ^[5] and a stepped-oxide structure ^[6].

The first structure, is suitable for analog circuits in which LDMOS occupies only a small part of the total chip area, such as motor control ICs, as it doesn’t require additional process steps but still increases Ron. The stepped-oxide structure is better for analog circuits where the LDMOS occupies a large area of the chip, such as motor driver ICs and DC-DC converters, as it has low Ron and is cost effective, even with additional process steps. As a result, a suitable LDMOS structure can be selected in respect of chip design or applications.

These solutions were realized by combining Toshiba’s know-how in transistor design with Japan Semiconductor’s process technologies accumulated through the automotive analog IC business. These capabilities also allowed the companies to confirm that design optimization of the stepped-oxide structure by TCAD simulation realizes a LDMOS that reduces Ron more effectively than conventional LDMOS. The companies will continue to research Ron and reliability and aim to bring the technology to analog power ICs by next year.

Toshiba Electronic Devices & Storage Corporation and Japan Semiconductor Corporation are committed to continuous R&D in semiconductor processes that deliver high value-added semiconductors offering high reliability and low stand-by power.