PCIM 2024

Toshiba investigated the impact of combining epoxy-potting encapsulation with an insulated metal substrate (IMS) on the performance and reliability of SiC MOSFET modules. Static and dynamic characteristics, thermal resistance, and power cycle tolerance were measured. The optimized copper pattern layout enabled the reduction of conduction loss in the IMS module. In addition, the IMS module showed improved power cycling tolerance compared with the conventional ceramic insulated substrate.

A 4.5 kV double-gate (DG) reverse-conducting (RC) press-pack injection-enhanced gate transistor (PP-IEGT: PPI) was developed. The fabricated DG-RC-PPI was examined under a 2800 V, 2100 A switching condition. By applying gate control, turn-off switching loss and reverse-recovery loss were reduced by 30% and 18%, respectively. As a result, we succeeded in reducing the total switching loss by 16% compared with a conventional single-gate PPI.

Speaker: Satoshi Yoshida recieved the B.S., M.S. and the Ph.D. degree in engineering from the university of Tokyo, Tokyo, Japan, in 2020. He joined Corporate Research and Development Center, Toshiba Corporation, Kanagawa, Japan, in 2020, where he has been working on the research and development of power electronics modules and packages.

Co-Authors: Tatsunori Sakano, Takahiro Kato, Atsushi Yamaoka, Tomoaki Inokuchi, Kazuto Takao Toshiba, JP; Ryohei Gejo, Toshiba Electronic Devices & Storage, JP

We parallel-connected SiC MOS modules with a rating of 3.3 kV/800 A confirmed the effect of the peripheral circuit parameters on the switching operation.The experimental results showed that fluctuation in Vgs could be suppressed by tying the gate wiring. The allowable increase in inductance of the main circuit was determined by simulation. As a result, It is important to design equal stray inductance, in order to align the imbalanced current within the range where turn-off surge is acceptable.

Co-Author: Shinichi Hiroshige, Toshiba Electronic Devices & Storage, JP

To unlock the full potential of power semiconductors, active gate drivers offer optimal driving patters, minimizing switching losses and overshoots for enhanced efficiency and EMC performance in various applications.

This presentation introduces a fully integrated digital active gate driver augmented with an artificial neural network for optimization. The on-chip ADC and 2n-sec gate current control enable surge current cancellation under various load current conditions. The programmable capabilities of the active gate driver includes optimizing driving patterns for switching transients and adjusting the short circuit protection feature (DESAT). Digitally tunable DESAT circuitry and adjustment algorithms achieve circuit parameter settings automatically that allow for false-positive short-circuit protection. While the on-chip lookup table ensures easy implementation, contributing to efficient and flexible SiC MOSFET-driven converter designs.