Toshiba Develops 48V-to-1V Non-Isolated DC-DC Converter IC

June 28, 2024

Toshiba Electronic Devices & Storage Corporation

Kawasaki, Japan ― Toshiba Electronic Devices & Storage Corporation (Toshiba) has developed an innovative star-delta switching topology that eliminates the need for a transformer for DC-DC converter ICs with 48V input and 1V output, and that achieves the industry’s highest current densities^[1] of up to 790 mA/mm², plus a high power conversion efficiency of up to 88%. The topology contributes to smaller, more efficient high-voltage DC-DC power supplies for high current applications.

Incremental rises in load currents in the DC-DC converters of server and data centers are increasing conduction losses^[2] of interconnects. Standardization to reduce the losses centers on raising the input voltage from 12V to 48V. However, for the current Buck topology, this requires the width of the pulses that drive the power switch to be four times shorter, and that increases switching losses that degrade power conversion efficiency. The mainstream solution is to use transformers in the isolated topologies to expand the driving pulse width, but they require a lot of space. Non-isolated hybrid topologies^[3] that use both inductors and capacitors able to reduce the volume by 10 to 100 times have emerged as an alternative, but one that requires the addition of 0.8 to 1.0 capacitors per pulse-width expansion ratio^[4]. This increases external components and congestion in external pin wiring, resulting in excessive mounting costs.

Toshiba has developed an innovative star-delta switching topology that merges the switching layers^[5] on the input side where the current is comparably small, and has reduced the capacitor count per pulse-width expansion ratio to 0.5 to 0.6 (Figure 1). When power is turned on, Steps 1 to 4 are repeated, with capacitors configured in a star network^[6] in Step 1 and in a delta network^[7] in Step 3. Each switching layer requires at least one capacitor, and optimizing the number of switching layers reduces the total number of capacitors (Figure 2). While the conventional method generates multiple equally-divided switching layers from the 48V input voltage, the new method merges the switching layers of low current, reducing the total number of capacitors. Toshiba has confirmed that although this merging requires the use of high-voltage switches, there is no obvious area expansion compared to multiple low-voltage switches in the conventional non-isolated hybrid topology, since the size of the switches can be minimized as the current is minimal.

Toshiba’s analysis of test chips with the topology confirmed the industry’s highest current densities^[1] of 730 to 790 mA/mm². This was achieved with the development of a bootstrap circuit with reduced capacitance, which reduced the layout area by up to 61% (Toshiba measurement). To further improve the conversion efficiency, Toshiba developed a level shifter circuit^[8] that can support an active bias current scheme, which reduces bias current by up to 92%, and confirmed power conversion efficiency of up to 88% (Figure 3) (Toshiba measurement). Toshiba will further refine the topology toward early product launch.

Toshiba presented the details of the technology at the 2024 IEEE Symposium on VLSI Technology & Circuits, an international semiconductor conference held in Hawaii, USA, from June 16 to 20.