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FFSA™ is an innovative custom SoC development platform that presents metal configurable standard cell logic gates, SRAM, high-speed SerDes protocols and input/output buffers capable of meeting the needs of diverse customers.


We have multiple masterslices with multiprotocol high-speed SerDes for each process and propose the optimal masterslice to meet the customer’s requirement.

Process technology 130nm 65nm 40nm 28nm
The maximum gate number(*) 912Kgate 21Mgate 25Mgate 100Mgate
Maximum SRAM capacity 664Kbit 19Mbit 30Mbit 207Mbit
Maximum transceiver speed 12.5Gbps 28Gbps
Number of the maximum transceiver lanes 14 64
The number of maximum I/O pins 337 1110 720 928

(*) The number of gates available is a guideline. It differs with the application.


Toshiba FFSA™ Overview

FFSA™ structure

The upper metal layers are reserved for customization, while the other layers are common to all customers . This enables a proportion of the device masks to be prepared in advance, thus reducing both development and production time, and allows the largest part of the overall cost to be shared among many different customizations, resulting in much lower NRE than for individual ASIC development.
By using ASIC development methodology and a cell library, its performance and power consumption level are nearly equivalent to those of ASIC.
Moreover, with customization limited to only a few metal layers, turnaround time of sample manufacturing and mass production can be shorter than for ASIC.

FFSA™ structure


FFSA™ can perform with more than double the frequency (SRAM) compared with the same process node FPGA.


Power consumption

FFSA™ can achieve 5 times the power efficiency compared with FPGA one process node ahead.

Power consumption

*The result varies depending on design and conditions.

FFSA™ technology IP application

FFSA™ metal configurable technology is applicable as an IP for ASIC development.
This means customers are able to develop their own original masterslices with a mix of highly optimized ASIC blocks and metal configurable FFSA™ blocks, and reuse the original masterslices to develop variants only with the change of metal layers, resulting in total NRE reduction and flexible ASIC-style implementation.

FFSA™ technology IP application

* All other company names, product names, and service names mentioned herein may be trademarks of their respective companies.


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·Before creating and producing designs and using, customers must also refer to and comply with the latest versions of all relevant TOSHIBA information and the instructions for the application that Product will be used with or for.