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Optimising MOSFET performance – chip and package

Optimising MOSFET performance – chip and package

The ongoing drive to improve power conversion performance while reducing system size and thermal dissipation is at the heart of today’s MOSFET development. And to achieve this, semiconductor manufacturers must consider both the underlying semiconductor processes and the packaging technology.

The image here shows the improvements in electrical performance brought about by some of the recent advances in device and package technology. As MOSFETs in the 5mm x 6mm footprint have evolved from UMOS VIII to UMOS IX-H technology, the new silicon has reduced RDS(ON) by 42%, while the lower DFPR of the DSOP Advance package is shown to be responsible for an additional 25% reduction. This diagram, of course, is concerned only with electrical performance and does not express the increased thermal capability of the DSOP Advance package.

Toshiba’s white paper on the latest silicon and package advances for power MOSFETs provides more information on the capabilities of these new technologies.

Click here to download the whitepaper

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·Before creating and producing designs and using, customers must also refer to and comply with the latest versions of all relevant TOSHIBA information and the instructions for the application that Product will be used with or for.