Thermal Management Implications of Advances in Packaging & Silicon Technologies for Power Semiconductor Devices

The importance of implementing adequate thermal management resources is increasing as higher density power technology is incorporated into system designs, but this also has repercussions. It leads to the utilising of value board space, the increasing of bill-of-materials costs and the raising overall system complexity. Furthermore, if the cooling mechanism is electro-mechanical in nature (such as a fan), it can also raise the power budget substantially.

OEMs are seeking out more effective ways to ensure that inside their products the amount of energy converted into heat is kept to a minimum. This will mean that such products can be placed into enclosures with smaller form factors (that are more attractive to consumers) and have higher power ratings that will thereby facilitate support for a greater breadth of features and functionality (which will mean that their products have the edge of those of their rivals). More has to be done at the component level to address OEM demands, but unfortunately things are in reality not that simple.

Keeping both power efficiency and switching speeds at acceptable levels has traditionally been a difficult (and at times frustrating) balancing act. Trying to maintain a low on-state resistance (R_DS(ON)) so that conduction performance is enhanced has normally meant compromising on the MOSFETs switching characteristics. Conversely, optimising the device to minimise gate charge (Qg) has allowed higher switching speeds to be benefited from, but has also heightened the R_DS(ON) and increased power losses once again - the trade-off between these two parameters being described via the device’s figure of merit (R_DS(ON) x Qg).

The progress being made in power semiconductor fabrication is now bringing about marked improvements in power conversion efficiencies. This means that less heat is generated. To complement this, the implementation of more sophisticated IC packaging is expediting the heat dissipation process. What is therefore needed is a two-pronged attack. From a silicon perspective, innovation is leading to improvements in power conversion efficiency and mitigating heat generation issues. At the same time more advanced packaging technology design is enabling heat to be removed from the system.

Toshiba’s latest generation UMOS are housed in DPAK+ packages which have the same dimensions and outline as the conventional DPAK format, but utilise copper clips (rather than aluminium bondwires) to connect the gate and source pins directly to the metallised electrodes on the die in order to combat power losses.

To learn more about Toshiba’s innovations in power IC design, download the following white paper: