Paralleling MOSFETs: Some key considerations

However, 'stable and uniform' can be more challenging than it might first appear. The PCB itself introduces unwanted ('parasitic') circuit elements that must be managed and designed for. Also, natural manufacturing variations in MOSFETs require consideration.

Individual device characteristics can vary within the tolerances of the datasheet specifications. The threshold voltage (V_th) is susceptible to variation and can cause current imbalance. Using MOSFETs from the same production lot or batch (with matched values of V_th) will reduce variations in current through each device.

When using external components, such as a gate resistor (R_g), tolerances will cause imbalance. However, the issue is not just the obvious components - all PCB traces have an element of resistance, inductance and capacitance. If there is a difference in the path length from the voltage source to the MOSFETs, this will also create imbalances. To address this, each gate pin trace must be kept as short as possible, thereby avoiding resistance accuracy problems and reducing the parasitic elements.

The same applies to power traces. Non-symmetrical traces here can cause destructive oscillations due to unbalanced impedances. Using surface-mount devices is one effective solution to decrease parasitic impedance, especially parasitic inductance.

Designing circuits with parallel MOSFETs is an important requirement in applications such as buck converters. The best solutions will be based on a careful selection of MOSFET devices and a methodical and balanced approach to circuit design. This is especially important in terms of managing the parasitic impedances that can occur in external resistances and PCB traces. Effectively addressing these issues can significantly simplify the implementation and effectiveness of parallel MOSFET architectures.

To find out more about important factors to consider when connecting MOSFETs in parallel click here: