3.2. Common-mode input voltage range (CMV_IN) and common-mode input signal rejection ratio (CMRR)

The common-mode input signal rejection ratio (CMRR) of a differential amplifier is a metric used to indicate its ability to reject two signals or noises (common-mode noise) that have the same amplitude and phase at V_IN(-) and V_IN(+). It is expressed by the following equation. Figure 3-5 shows a test circuit for the common-mode input signal rejection ratio.
The common-mode input voltage range (CMV_IN) is defined as the input voltage range in which the prescribed CMRR is satisfied under the prescribed conditions. The datasheets for Toshiba’s op-amps specify the CMRR value under DC conditions.

where V_IN1 and V_IN2 are the maximum and minimum CMV_IN values, respectively, and V_OUT1 and V_OUT2 are the output (V_O) voltages at V_IN1 and V_IN2, respectively.
As can be seen from Figure 3-5, the input offset voltage (V_IO) discussed in the previous section is the CMRR value under a special condition (V_IN = V_DD/2).

The op-amp operates as described in Section 1.2. The differential input pair of a typical op-amp is composed of P-channel MOSFETs as shown in Figure 3-6. As the V_IN(+) and V_IN(-) voltages increase, the drain-source voltage of Q_p3 in the current source decreases, causing the current flowing to the differential input pair and the current mirror to decrease slightly. Figure 3-7 shows an example of I_D-V_DS curves for a discrete P-channel MOSFET. Suppose, for example, that V_DS = -1.5 V and I_D = 80 mA initially. As the drain current of the MOSFET decreases, its drain-source voltage changes nonlinearly in the saturation region.
Although the internal devices of an op-amp IC are placed and fabricated in such a manner as to make the MOSFETs uniform, they are not perfectly symmetrical at the micro level. In addition, semiconductor chips are mounted on a metal frame in a package and soldered onto a printed circuit board. Therefore, the mechanical stress applied to each element of an op-amp IC differs slightly. These factors cause a slight difference in threshold voltage among the P-channel MOSFETs of the differential input pair. Therefore, a decrease in drain current causes different nonlinear changes in their drain-source voltage. As a result, the input offset voltage has a slope with respect to the input voltage (V_IN) in the common-mode input voltage range as shown in Figure 3-8. Therefore, the CMRR values are calculated at the maximum and minimum common-mode input voltages.