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Calculating the Operating Supply Current and Power Dissipation

Calculating the power dissipation of a CMOS logic IC

FAQ : How can I calculate the power dissipation of general-purpose logic ICs

Power dissipation should be calculated from both of the following:

Static supply current
Dynamic supply current

Power can be obtained by multiplying current by the voltage applied to an IC.

Static power dissipation: P_SWhile CMOS logic is in a static state (i.e., while its input voltage remains almost unchanged), little current flows in it except tiny leakage current that flows across the internal reverse-biased pn junction (known as static supply current, I_CC). Static power dissipation is I_CC multiplied by the supply voltage.
P_S= V_CC x I_CCV_CC: Voltage applied to a logic IC
I_CC: Static supply current shown in the datasheet

Dynamic power dissipation: P_L+P_PDDynamic supply current is the current that flows in CMOS logic ICs while its input transitions between High and Low. This current flows during the charging and discharging of capacitance. It is necessary to consider both parasitic capacitance (internal equivalent capacitance) and load capacitance.
Dynamic power dissipation is dynamic supply current multiplied by the voltage applied to the p-channel or n-channel MOSFET.
For the sake of simplicity, the following calculation assumes that this voltage is equal to V_CC at which dynamic supply current becomes the maximum.

Dynamic power dissipation due to C(L) — Dynamic power dissipation due to C_L

Dynamic power dissipation due to load capacitance (C_L): P_LP_L means power dissipation when an external load is charged and discharged as shown by the right-hand figure.
The amount of charge (Q_L) stored on the load capacitance is calculated as follows:
Q_L = C_L * V_CCC_L: Load capacitance
Let the output signal frequency be f_OUT (= 1/T_OUT). Then, the average current (I_L) is expressed as follows:
I_L = Q_L / T = C_L * V_CC * f_OUTHence, dynamic power dissipation (P_L) is:
P_L = V_CC * I_L ＝ C_L * V_CC^2 * f_OUTIf an IC has multiple outputs, its dynamic power dissipation can be calculated as follows:
P_L = V_CC^2 * Σ (C_Ln* f_OUTn)

Dynamic power dissipation due to C(PD) — Dynamic power dissipation due to C_PD

Dynamic power dissipation due to internal equivalent capacitance (C_PD): P_PDCMOS logic ICs have various parasitic capacitances as shown by the right-hand figure. These capacitances are equivalently expressed as C_PD. (Actually, C_PD is calculated from power dissipation at relatively high frequency (1 MHz) under a zero-load condition.)
P_PD is the power dissipated by the equivalent capacitance of an IC and can be considered in the same manner as P_L.
Note, however, that P_PD is calculated at input frequency (f_IN):
P_PD ＝ V_CC* I_L ＝ C_PD * V_CC^2 * f_IN

Total power dissipation (P_TTL) can be obtained as the sum of static power dissipation (P_S) and dynamic power dissipation (P_L + P_PD):
P_TTL＝ P_S + P_L + P_PD