# Calculating the Operating Supply Current and Power Dissipation

Calculating the power dissipation of a CMOS logic IC

Power dissipation should be calculated from both of the following:

• Static supply current
• Dynamic supply current

Power can be obtained by multiplying current by the voltage applied to an IC.

Static power dissipation: PS
While CMOS logic is in a static state (i.e., while its input voltage remains almost unchanged), little current flows in it except tiny leakage current that flows across the internal reverse-biased pn junction (known as static supply current, ICC). Static power dissipation is ICC multiplied by the supply voltage.
PS = VCC x ICC
VCC: Voltage applied to a logic IC
ICC: Static supply current shown in the datasheet

Dynamic power dissipation: PL+PPD
Dynamic supply current is the current that flows in CMOS logic ICs while its input transitions between High and Low. This current flows during the charging and discharging of capacitance. It is necessary to consider both parasitic capacitance (internal equivalent capacitance) and load capacitance.
Dynamic power dissipation is dynamic supply current multiplied by the voltage applied to the p-channel or n-channel MOSFET.
For the sake of simplicity, the following calculation assumes that this voltage is equal to VCC at which dynamic supply current becomes the maximum.

Dynamic power dissipation due to load capacitance (CL): PL
PL means power dissipation when an external load is charged and discharged as shown by the right-hand figure.
The amount of charge (QL) stored on the load capacitance is calculated as follows:
QL = CL * VCC
Let the output signal frequency be fOUT (= 1/TOUT). Then, the average current (IL) is expressed as follows:
IL = QL / T = CL * VCC * fOUT
Hence, dynamic power dissipation (PL) is:
PL = VCC * IL ＝ CL * VCC^2 * fOUT
If an IC has multiple outputs, its dynamic power dissipation can be calculated as follows:
PL = VCC^2 * Σ (CLn* fOUTn)

Dynamic power dissipation due to internal equivalent capacitance (CPD): PPD
CMOS logic ICs have various parasitic capacitances as shown by the right-hand figure. These capacitances are equivalently expressed as CPD. (Actually, CPD is calculated from power dissipation at relatively high frequency (1 MHz) under a zero-load condition.)
PPD is the power dissipated by the equivalent capacitance of an IC and can be considered in the same manner as PL.
Note, however, that PPD is calculated at input frequency (fIN):
PPD ＝ VCC * IL ＝ CPD * VCC^2 * fIN

Total power dissipation (PTTL) can be obtained as the sum of static power dissipation (PS) and dynamic power dissipation (PL + PPD):
PTTL＝ PS + PL + PPD

## Usage Considerations of CMOS Logic ICs

Handling of Unused Input Pins
Input Rise and Fall Time Specifications
Multiple Outputs from a General-Purpose CMOS Logic IC Come Into Conflict (Short-Circuiting)
Connecting a Load Capacitance to a CMOS Output Pin
Level Shifting Using an Input-Tolerant Function
Example of Application of the Power-Down Protection Function (Partial Power-Down)
Input-Tolerant and Output Power-Down Protection Functions Available with Each Series
Types of Noise to be Noted
Countermeasures for Reducing Switching Noise
Countermeasures for Signal Reflection
Countermeasures for Crosstalk
Countermeasures for Hazards
Countermeasures for Metastability
Countermeasures for Latch-Up
Countermeasures for ESD Protection

## Related information

• Application Notes
• FAQ
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