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Countermeasures for Latch-Up

A latch-up is a phenomenon specific to CMOS integrated circuits that is caused by SCR (Silicon Controlled Rectifier) generation.
Let’s consider a CMOS logic IC formed on an n-substrate. A CMOS logic IC has various parasitic bipolar transistors (Q1 to Q6), internally forming a triac circuit. A common cause of a latch-up is excessive noise, surge voltage, or surge current on an input or output pin of a CMOS IC. Another cause is a sharp change in the supply voltage. In such cases, the internal triac circuit turns on, causing an excessive current to continue flowing between V_CCand GND even if the triggering signal is disconnected, and eventually leading to the destruction of the IC.

Equivalent circuit for a typical CMOS logic IC with parasitic elements

The following briefly describes the process leading to a latch-up.
The below figure shows an equivalent circuit of a CMOS circuit, including its parasitic structure. An NPN transistor (Q2) is formed in the p-well on the n-channel MOSFET side while a PNP transistor (Q1) is formed in the n-substrate on the p-channel MOSFET side. Parasitic resistances (R_S and R_W) also exist between IC pins. Parasitic elements (Q1 and Q2) form a thyristor.

For example, if current flows into the n-substrate because of an external cause, a voltage drop occurs across resistor R_S in the n-substrate. As a result, Q1 turns on, causing current to flow from V_CC to GND via resistor R_W in the p-well. The current flowing through R_W produces a voltage difference across R_W, which turns on Q2, causing supply current to flow via R_S. Since this further increases the voltage difference across R_S, Q1 and Q2 remain on. Consequently, the supply current continues increasing. As described above, CMOS ICs suffer from a latch-up problem when voltage differences occur across R_W in the p-well and R_S in the n-substrate.

Countermeasure for latch-up
Use under the rated conditions.
But it is recommended to add a protection circuit to the IC interface as shown in below figure.
if an excessive surge might be applied to the IC.