Sequential Logic: Shift Registers

Shift registers
Examples: 74VHC164, 74VHC165

Shift registers can be configured for serial-parallel (SI-PO) or parallel-serial (PI-SO) conversion.
Parallel-serial conversion helps reduce the number of transmission lines (i.e., transmission bit width). Some shift registers have the CLR input that is used to initialize the internal state to a known value.
The following shows the logic symbol and truth table of a shift register.
A shift register is composed of multiple flip-flops.

Operation of a shift register

The following describes the operation of a shift register using a logic schematic and a timing diagram. A shift register is composed of a cascade of flip-flops in which the output (Q) of each flip-flop is connected to the data (D) input of the next flip-flop in the chain.
A serial input (SI) is applied to the data (D) input of the first flip-flop. The data from SI are latched on the rising edge of the clock (CK) and appear at QA. With four clock pulses, the data from SI are transferred to the fourth flip-flop. As a result, the serial input (SI) is converted to parallel output data appearing at QD, QC, QB, and QA.

Types of shift registers
Logic schematic of the 74VHC164 eight-bit SI-PO shift register

Logic schematic of the 74VHC165 eight-bit PI-SO shift register