Operation of a shift register
The following describes the operation of a shift register using a logic schematic and a timing diagram. A shift register is composed of a cascade of flip-flops in which the output (Q) of each flip-flop is connected to the data (D) input of the next flip-flop in the chain.
A serial input (SI) is applied to the data (D) input of the first flip-flop. The data from SI are latched on the rising edge of the clock (CK) and appear at QA. With four clock pulses, the data from SI are transferred to the fourth flip-flop. As a result, the serial input (SI) is converted to parallel output data appearing at QD, QC, QB, and QA.