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The information presented in this cross reference is based on TOSHIBA's selection criteria and should be treated as a suggestion only. Please carefully review the latest versions of all relevant information on the TOSHIBA products, including without limitation data sheets and validate all operating parameters of the TOSHIBA products to ensure that the suggested TOSHIBA products are truly compatible with your design and application.
Please note that this cross reference is based on TOSHIBA's estimate of compatibility with other manufacturers' products, based on other manufacturers' published data, at the time the data was collected.
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Decoders
Example: VHC138
A decoder converts binary information from the N coded inputs to a maximum of 2N unique outputs. It is commonly used to increase the number of ports and generate chip select signals.
Operation of a decoder
The following shows a logic symbol, truth table, and timing diagram of a 3-to-8 decoder, i.e., a decoder with three inputs and eight outputs.
The following shows how a 3-to-8 decoder is used to generate eight chip select signals from three inputs (A, B, and C). When A, B, and C are all Low, only the /Y0 output provides a logic Low, causing IC0 to be selected.
This figure indicates that, with a combination of three inputs, an arbitrary chip can be selected from up to eight chips.