Part Number Search

Cross Reference Search

About information presented in this cross reference

The information presented in this cross reference is based on TOSHIBA's selection criteria and should be treated as a suggestion only. Please carefully review the latest versions of all relevant information on the TOSHIBA products, including without limitation data sheets and validate all operating parameters of the TOSHIBA products to ensure that the suggested TOSHIBA products are truly compatible with your design and application.
Please note that this cross reference is based on TOSHIBA's estimate of compatibility with other manufacturers' products, based on other manufacturers' published data, at the time the data was collected.
TOSHIBA is not responsible for any incorrect or incomplete information. Information is subject to change at any time without notice.

Keyword Search

Parametric Search

Stock Check & Purchase

Select Product Categories

Sequential Logic: Shift Registers

Logic symbol and truth table of a shift register
Logic symbol and truth table of a shift register

Shift registers
Examples: 74VHC164, 74VHC165

Shift registers can be configured for serial-parallel (SI-PO) or parallel-serial (PI-SO) conversion.
Parallel-serial conversion helps reduce the number of transmission lines (i.e., transmission bit width). Some shift registers have the CLR input that is used to initialize the internal state to a known value.
The following shows the logic symbol and truth table of a shift register.
A shift register is composed of multiple flip-flops.

Operation of a shift register

The following describes the operation of a shift register using a logic schematic and a timing diagram. A shift register is composed of a cascade of flip-flops in which the output (Q) of each flip-flop is connected to the data (D) input of the next flip-flop in the chain.
A serial input (SI) is applied to the data (D) input of the first flip-flop. The data from SI are latched on the rising edge of the clock (CK) and appear at QA. With four clock pulses, the data from SI are transferred to the fourth flip-flop. As a result, the serial input (SI) is converted to parallel output data appearing at QD, QC, QB, and QA.

Logic schematic of a shift register
Logic schematic of a shift register
Timing diagram of a shift register (Serial-in, parallel-out)
Timing diagram of a shift register (Serial-in, parallel-out)
Logic schematic of the 74VHC164 eight-bit SI-PO shift register

Types of shift registers
Logic schematic of the 74VHC164 eight-bit SI-PO shift register

Logic schematic of the 74VHC165 eight-bit PI-SO shift register

Logic schematic of the 74VHC165 eight-bit PI-SO shift register

There are serial-in/parallel-out and parallel-in/serial-out shift registers.

Chapter3 Basic CMOS Logic ICs

Basic CMOS Logic ICs
Combinational Logic: Inverters and Buffers
Combinational Logic: Bidirectional Bus Buffers
Combinational Logic: Schmitt-Trigger Devices
Combinational Logic: Decoders
Combinational Logic: Multiplexers
Combinational Logic: Analog Multiplexer/Demultiplexers
Combinational Logic: Analog Switches
Sequential Logic: Latches
Sequential Logic: Flip-Flops
Sequential Logic: Counters

Products

Related information

A new window will open