NVIC control registers are accessed as devices located from the main core to the memory.
- control the setting and clearing of each interrupt enable
- control the setting and clearing of each interrupt request (Release of hold)
- control the priority of interrupts
Let's see the control of external interrupt processing, which is one of the basic functions of the NVIC block.
The Enable bit and Pend bit are assigned to each external interrupt signal, and configure the control registers which are divided into a set-only register and a clear-only register.
External interrupt generation is controlled by the information of the Priority register that sets the interrupt priority and the status of the Enable bit and Pend bit.