NVIC (Nested Vectored Interrupt Controller)

The NVIC block suspends the calculation processing that is running on the main core, and controls switching to prioritized processing.
It supports the system exception and interrupt occurrence.
If a high-priority exception interrupt is required during exception processing, then the NVIC block:

1) Suspends the exception being processed
2) Starts high-priority exception processing
3) Completes high priority exception processing
4) Resumes interrupted exception processing

It can control the nest, i.e. the exception interrupt processing.
It also includes the debug control function and SysTickTimer, which is a hardware timer for the operating system (OS) to manage tasks.

NVIC(Nested Vectored Interrupt Controller)

[Fe] Fetch stage
[De] Decode stage
[Ex] Execution stage
[MUL/DIV] Multiplication/Division

Chapter 2 Arm® Cortex®-M3

Hardware Configuration
Main Core
Register Configuration
The Role of the Register
Stack Pointer
PUSH/POP to the Stack Pointer
Special Register
Operation Mode and Stack Pointer (1)
Operation Mode and Stack Pointer (2)
Exceptions (Reset, Interrupt, Fault, System Call)
The Role of NVIC
Tail Chain Control by NVIC
Memory Map
Memory Map for Arm® Cortex®-M3 Specifications
Memory Map of TMPM330: Example of TX03 Series
Vector Table (1)
Vector Table (2)
Bit Band Area and Bit Band Alias Area (1)
Bit Band Area and Bit Band Alias Area (2)

* Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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