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The Role of NVIC

The Role of NVIC

NVIC control registers are accessed as devices located from the main core to the memory.

  • control the setting and clearing of each interrupt enable
  • control the setting and clearing of each interrupt request (Release of hold)
  • control the priority of interrupts

Let's see the control of external interrupt processing, which is one of the basic functions of the NVIC block.
The Enable bit and Pend bit are assigned to each external interrupt signal, and configure the control registers which are divided into a set-only register and a clear-only register.
External interrupt generation is controlled by the information of the Priority register that sets the interrupt priority and the status of the Enable bit and Pend bit.

Chapter 2 Arm® Cortex®-M3

Hardware Configuration
NVIC (Nested Vectored Interrupt Controller)
Main Core
Register Configuration
The Role of the Register
PC, LR
Stack Pointer
PUSH/POP to the Stack Pointer
Special Register
Operation Mode and Stack Pointer (1)
Operation Mode and Stack Pointer (2)
Exceptions (Reset, Interrupt, Fault, System Call)
Tail Chain Control by NVIC
Memory Map
Memory Map for Arm® Cortex®-M3 Specifications
Memory Map of TMPM330: Example of TX03 Series
Vector Table (1)
Vector Table (2)
Bit Band Area and Bit Band Alias Area (1)
Bit Band Area and Bit Band Alias Area (2)

* Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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