What are the considerations when using MOSFETs in parallel?

Power MOSFETs are sometimes used in parallel in order to support high power or reduce loss by reducing the on-resistance of the power MOSFET. In this case, it is important to ensure that current flows evenly to each device. If the current becomes unbalanced, excessive current may flow to some devices, destroying the elements. This current unbalance must be taken into consideration both during steady conduction and during switching.

Measures against imbalance during steady-state conduction (steady state)
Differences in the on-resistance RDS(on) of elements connected in parallel, or differences in the resistance of the board or wiring, can cause an imbalance in the drain current, which can destroy the elements. This difference in drain current also affects the current value and transient loss during switching. The on-resistance RDS(on) of a MOSFET has a positive temperature coefficient (see Fig. 1). Therefore, even if there is a temperature difference between devices, the risk due to heat generation conditions are not particularly large, because the current flowing to the hotter device is suppressed. Measures include the following:

  1. Use MOSFETs with no RDS(on) variation, such as using products from the same lot.
  2. Optimize the board layout (match the resistance components of the wiring).
Fig. 1 RDS(on) temperature characteristics: The on-resistance (RDS(on)) of a MOSFET has a positive temperature characteristic.
Fig. 1 RDS(on) temperature characteristics (TK040N60Z1)
Fig. 2 Vth temperature characteristics: The Vth of a MOSFET has negative temperature characteristics.
Fig. 2. Vth temperature characteristics (TK040N60Z1)
Fig. 3 Gate resistors for prevent oscillation: A diagram showing the configuration of gate resistors inserted in each gate as a countermeasure against MOSFET oscillation.
Fig. 3 Gate resistor for preventing oscillation

Countermeasures for imbalance during switching (transient state)
When a device is switching (transient state), in addition to the unbalance factors in the steady state, an imbalance in the drain current occurs due to the difference in Vth of devices connected in parallel and the difference in inductance components of the board and wiring. Also, because Vth has a negative temperature coefficient (see Fig. 2), the Vth of an element whose temperature has risen drops further. This causes further current imbalance. Also, parallel connection can cause not only current imbalance but also oscillation. Countermeasures include the following.

  1. Use MOSFETs with no Vth variation, such as using products from the same lot.
  2. Optimize the board layout (match the resistance and inductance components of the wiring).
  3. Insert a series resistor in the gate of each MOSFET to prevent oscillation. *1 (Fig. 3)
  4. Match the heat dissipation conditions of each element.

In addition, overshoot during switching can cause the MOSFET to break down. In this case, caution is required as product variations can cause all the current to concentrate on an element with a low drain withstand voltage, destroying it.

The following application note also contains information on oscillation, etc. Please refer to it.

When connecting MOSFETs in parallel in this way, care must be taken, just as with bipolar transistors (BJTs). When it comes to imbalance in the steady state, MOSFETs are less likely to experience thermal runaway than BJTs because the temperature characteristic of their on-resistance is positive. However, because MOSFETs have fast switching speeds, more care must be taken with imbalance during switching than with BJTs.

*1: Compared to using a single power MOSFET, parasitic oscillation is more likely to occur when used in parallel. Even if oscillation does not occur, oscillating waveforms such as overshoot and undershoot may be seen at the gate. This is caused by voltage oscillation due to drain wiring inductance during switching (especially when turning off), and a resonant circuit caused by the gate-drain capacitance and gate wiring inductance. Parasitic oscillation can be suppressed by connecting a resistor to the gate of each MOSFET connected in parallel. This countermeasure is also effective in preventing overshoot. See Fig. 3. 

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