Correct drive for IGBTs and SiC MOSFETs enhances control and protection

The importance of switching devices is growing as many applications (such as EVs and renewable energy) rely on attaining previously unachievable levels of efficiency. Innovations in switching devices are allowing faster operation that, when implemented correctly, allow these lofty goals to be achieved.

Driving the gates of IGBTs, silicon MOSFETs and silicon carbide (SiC) MOSFETs correctly in high-frequency switching applications like EV-charging is vital for efficiency and reliability. Devices such as integrated smart gate drivers simplify this as they often include a Miller clamp and overcurrent detection using a ‘DESAT’ feature.

While IGBTs and Si/SiC MOSFETs are nominally off at V_GS = 0V, their gate is often driven to a negative voltage for the OFF state, typically -7V for IGBTs and sometimes -5V for SiC MOSFETs. The reason for this is to prevent injected current entering the gate from the non-linear Miller capacitance, between collector/drain and gate, which occurs as the device switches off.

An alternative approach involves the use of a ‘Miller clamp’ – a separate MOSFET that shorts gate to emitter/source after the main drive signal has transitioned below a pre-determined level. The drive to the Miller clamp transistor must be carefully timed with the PWM OFF-signal to be effective. After the collector/drain has stabilised at its OFF-state voltage, the Miller clamp transistor can be switched off. The timing of this is not critical provided it is off before the next ON-state drive. If the negative gate drive voltage can be reduced or eliminated by using a Miller clamp circuit, the complexity of the required power supply is reduced and some valuable gate drive power is saved, contributing to enhanced efficiency.

Inadequate drive or an overload can cause power device failure, caused by the IGBT or SiC MOSFET coming out of saturation, dropping excess voltage and failing from over-dissipation. The driver can detect this condition by monitoring the collector/drain voltage of the device and if this can be interpreted as a fault, the driver will then immediately force the device off.

The technique is known as de-saturation detection or DESAT. The reaction time must be very rapid, as modern power devices are rated to withstand conditions such as short circuits for only a few microseconds.

The degree of integration now achieved in smart gate drivers allows designers to fit the parts as pre-certified and tested subsystems with performance that would be difficult to achieve with a discrete design. Comprehensive fault detection and reporting is built-in as effectively a single part, and reliability is extremely high. We prepared a whitepaper looking at the configuration of smart gate driver features. Access the paper here: