I2C Bus Interface – An Overview

I2C Bus Interface – An Overview

When it was devised four decades ago, the inter-integrated Circuit (I2C) interface was designed as a serial bus system for short-distance communication between microcontrollers and on-board peripherals. Based on its success, it helped to define system management bus (SMBus) for computer motherboards, and (PMBus) for components within power systems.

With just two signals, a serial data (SDA) line and a serial clock line (SCL), this single-ended synchronous interfacing technology only requires two wires. However, as the protocol calls for bi-directional communication designers require a degree of ingenuity when implementing any isolation circuitry.

I2C is typically used with an MCU or system-on-chip (SoC), and one or more target devices. The controller’s I2C pins are open drain meaning a resistor is required to pull the signals high, but this does avoid bus contention between two controllers.

The SDA signal is bi-directional. When implemented, the controller places its data on the SDA line to first select the target to be addressed. It is then used to select the register to access within that target. Once complete, the target returns the requested data over the SDA line. Targets also use the SDA line to acknowledge correct reception of the request (ACK) by holding SDA low or deny correct reception (NACK) by letting SDA be pulled high.

The SCL line is driven by the controller, defining the communication speed on the bus. Originally, I2C supported 100 kHz but, over the years, incremental improvements have increased this to 5 MHz. A target that requires more time can control the SCL signal together with the SDA - a feature known as clock stretching. Therefore, even with an isolated I2C interface, it is essential that bi-directional communication is supported.

I2C was only ever intended to be used for board-level communication, meaning that latencies within the isolation circuitry can hamper proper operation. According to the specification, the ACK/NACK signal must be valid after a setup time of 0.45µs in fast mode plus operation (1MHz). Also, in fast mode plus a target is expected to set up the SDA signal within 50ns after the falling edge of the previous clock bit.

Toshiba offers a range of high speed, low latency optoisolators (such as it TLP2362) that, if put in the right circuit, support bi-directional communication for isolated I2C interfaces.

To view the whitepaper on using optocouplers to isolate the I2C bus, please click here:

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