3-2-4. Combinational Logic: Decoders


Decoders
Example: VHC138
A decoder converts binary information from the N coded inputs to a maximum of 2N unique outputs. It is commonly used to increase the number of ports and generate chip select signals.


Operation of a decoder
The following shows a logic symbol, truth table, and timing diagram of a 3-to-8 decoder, i.e., a decoder with three inputs and eight outputs.

Logic symbol and truth table of a 3-to-8 decoder
Logic symbol and truth table of a 3-to-8 decoder
Timing diagram of a 3-to-8 decoder
Timing diagram of a 3-to-8 decoder
Generating chip select signals
Generating chip select signals

The following shows how a 3-to-8 decoder is used to generate eight chip select signals from three inputs (A, B, and C). When A, B, and C are all Low, only the /Y0 output provides a logic Low, causing IC0 to be selected.
This figure indicates that, with a combination of three inputs, an arbitrary chip can be selected from up to eight chips.

Chapter3 Basic CMOS Logic ICs

3-1. Basic CMOS Logic ICs
3-2-1. Combinational Logic: Inverters and Buffers
3-2-2. Combinational Logic: Bidirectional Bus Buffers
3-2-3. Combinational Logic: Schmitt-Trigger Devices
3-2-5. Combinational Logic: Multiplexers
3-2-6. Combinational Logic: Analog Multiplexer/Demultiplexers
3-2-7. Combinational Logic: Analog Switches
3-3-1. Sequential Logic: Latches
3-3-2. Sequential Logic: Flip-Flops
3-3-3. Sequential Logic: Counters
3-3-4. Sequential Logic: Shift Registers

Products

Related information

A new window will open