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Combinational Logic: Decoders

Example: VHC138
A decoder converts binary information from the N coded inputs to a maximum of 2N unique outputs. It is commonly used to increase the number of ports and generate chip select signals.

Operation of a decoder
The following shows a logic symbol, truth table, and timing diagram of a 3-to-8 decoder, i.e., a decoder with three inputs and eight outputs.

Logic symbol and truth table of a 3-to-8 decoder
Logic symbol and truth table of a 3-to-8 decoder
Timing diagram of a 3-to-8 decoder
Timing diagram of a 3-to-8 decoder
Generating chip select signals
Generating chip select signals

The following shows how a 3-to-8 decoder is used to generate eight chip select signals from three inputs (A, B, and C). When A, B, and C are all Low, only the /Y0 output provides a logic Low, causing IC0 to be selected.
This figure indicates that, with a combination of three inputs, an arbitrary chip can be selected from up to eight chips.

Chapter3 Basic CMOS Logic ICs

Basic CMOS Logic ICs
Combinational Logic: Inverters and Buffers
Combinational Logic: Bidirectional Bus Buffers
Combinational Logic: Schmitt-Trigger Devices
Combinational Logic: Multiplexers
Combinational Logic: Analog Multiplexer/Demultiplexers
Combinational Logic: Analog Switches
Sequential Logic: Latches
Sequential Logic: Flip-Flops
Sequential Logic: Counters
Sequential Logic: Shift Registers


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