A latch-up is a phenomenon specific to CMOS integrated circuits that is caused by SCR (Silicon Controlled Rectifier) generation.
Let’s consider a CMOS logic IC formed on an n-substrate. A CMOS logic IC has various parasitic bipolar transistors (Q1 to Q6), internally forming a triac circuit. A common cause of a latch-up is excessive noise, surge voltage, or surge current on an input or output pin of a CMOS IC. Another cause is a sharp change in the supply voltage. In such cases, the internal triac circuit turns on, causing an excessive current to continue flowing between VCC and GND even if the triggering signal is disconnected, and eventually leading to the destruction of the IC.