Countermeasures for Latch-Up

A latch-up is a phenomenon specific to CMOS integrated circuits that is caused by SCR (Silicon Controlled Rectifier) generation.
Let’s consider a CMOS logic IC formed on an n-substrate. A CMOS logic IC has various parasitic bipolar transistors (Q1 to Q6), internally forming a triac circuit. A common cause of a latch-up is excessive noise, surge voltage, or surge current on an input or output pin of a CMOS IC. Another cause is a sharp change in the supply voltage. In such cases, the internal triac circuit turns on, causing an excessive current to continue flowing between VCC and GND even if the triggering signal is disconnected, and eventually leading to the destruction of the IC.

Equivalent circuit for a typical CMOS logic IC with parasitic elements 
Equivalent circuit for a typical CMOS logic IC with parasitic elements 

The following briefly describes the process leading to a latch-up.
The below figure shows an equivalent circuit of a CMOS circuit, including its parasitic structure. An NPN transistor (Q2) is formed in the p-well on the n-channel MOSFET side while a PNP transistor (Q1) is formed in the n-substrate on the p-channel MOSFET side. Parasitic resistances (RS and RW) also exist between IC pins. Parasitic elements (Q1 and Q2) form a thyristor.

For example, if current flows into the n-substrate because of an external cause, a voltage drop occurs across resistor RS in the n-substrate. As a result, Q1 turns on, causing current to flow from VCC to GND via resistor RW in the p-well. The current flowing through RW produces a voltage difference across RW, which turns on Q2, causing supply current to flow via RS. Since this further increases the voltage difference across RS, Q1 and Q2 remain on. Consequently, the supply current continues increasing. As described above, CMOS ICs suffer from a latch-up problem when voltage differences occur across RW in the p-well and RS in the n-substrate.

Countermeasures for latch-up

Countermeasure for latch-up
Use under the rated conditions.
But it is recommended to add a protection circuit to the IC interface as shown in below figure.
if an excessive surge might be applied to the IC.


Handling of Unused Input Pins
Input Rise and Fall Time Specifications
Multiple Outputs from a General-Purpose CMOS Logic IC Come Into Conflict (Short-Circuiting)
Connecting a Load Capacitance to a CMOS Output Pin
Calculating the Operating Supply Current and Power Dissipation
Level Shifting Using an Input-Tolerant Function
Example of Application of the Power-Down Protection Function (Partial Power-Down)
Input-Tolerant and Output Power-Down Protection Functions Available with Each Series
Types of Noise to be Noted
Countermeasures for Reducing Switching Noise
Countermeasures for Signal Reflection
Countermeasures for Crosstalk
Countermeasures for Hazards
Countermeasures for Metastability
Countermeasures for ESD Protection


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