2-2. NVIC (Nested Vectored Interrupt Controller)

The NVIC block suspends the calculation processing that is running on the main core, and controls switching to prioritized processing.
It supports the system exception and interrupt occurrence.
If a high-priority exception interrupt is required during exception processing, then the NVIC block:

1) Suspends the exception being processed
2) Starts high-priority exception processing
3) Completes high priority exception processing
4) Resumes interrupted exception processing

It can control the nest, i.e. the exception interrupt processing.
It also includes the debug control function and SysTickTimer, which is a hardware timer for the operating system (OS) to manage tasks.

NVIC(Nested Vectored Interrupt Controller)

[Fe] Fetch stage
[De] Decode stage
[Ex] Execution stage
[MUL/DIV] Multiplication/Division

Chapter 2 Arm® Cortex®-M3

2-1. Hardware Configuration
2-3. Main Core
2-4. Register Configuration
2-5. The Role of the Register
2-6. PC, LR
2-7. Stack Pointer
2-8. PUSH/POP to the Stack Pointer
2-9. Special Register
2-10-1. Operation Mode and Stack Pointer (1)
2-10-2. Operation Mode and Stack Pointer (2)
2-11. Exceptions (Reset, Interrupt, Fault, System Call)
2-12. The Role of NVIC
2-13. Tail Chain Control by NVIC
2-14. Memory Map
2-15. Memory Map for Arm® Cortex®-M3 Specifications
2-16. Memory Map of TMPM330: Example of TX03 Series
2-17-1. Vector Table (1)
2-17-2. Vector Table (2)
2-18-1. Bit Band Area and Bit Band Alias Area (1)
2-18-2. Bit Band Area and Bit Band Alias Area (2)

* Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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