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Fanout is the number of CMOS logic inputs that can be driven by one CMOS logic output. Therefore, fanout is equal to the output current of the driving IC divided by the input current of the driven ICs:

Fanout = IOH / IIH or IOL / IIL

This calculation used to have a significant meaning for TTL logic ICs that were commonly used before the advent of CMOS logic ICs. However, since the DC input current of the current CMOS logic ICs is on the order of microamperes, input current does not impose a major constraint on fanout.

In the case of CMOS logic ICs, the capacitance of the driven ICs acts as a limiting factor. Generally, it is not recommended to intentionally connect large capacitance to the output of a CMOS logic IC.  Typically, the input capacitance of a CMOS logic IC is on the order of 10 pF. (It depends on the product family. See the datasheet.) The sum of the capacitances that can be connected to an output of a CMOS logic IC is specified to be up to 500 pF.
(See the FAQ entry, “Is it OK to connect a capacitor to an output?“)

Therefore, up to 50 CMOS logic ICs can be connected to an output of a CMOS logic IC. However, care should be exercised as to the following:

 The rising slope of the signal waveform becomes shallow, increasing the propagation delay time.
(The propagation delay times shown in the datasheet are measured with an output capacitance of 50 pF.)

An increase in load capacitance (i.e., the sum of the input capacitances of the driven ICs) causes an increase in current consumption due to charging and discharging. 
(See the FAQ entry, “How can I calculate the power dissipation of general-purpose logic ICs?”)

Therefore, perform a board evaluation in advance to ensure that CMOS logic ICs work properly.

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