Power dissipation should be calculated from both of the following:
- Static supply current
- Dynamic supply current
Power dissipation can be obtained by multiplying the above current by the voltage applied to an IC.
Static power dissipation: PS
While CMOS logic Ics are in a static state (i.e., while its input signal remains unchanged), little current flows in it except tiny leakage current that flows across the internal reverse-biased pn junction (known as static supply current, ICC). Static power dissipation is ICC multiplied by the supply voltage.
PS = VCC x ICC
VCC: Voltage applied to a logic IC
ICC: Static supply current shown in the datasheet
Dynamic power dissipation
Dynamic supply current is the current that flows in CMOS logic while its input transitions between High and Low. This current flows during the charging and discharging of capacitance. It is necessary to consider both parasitic capacitance (internal equivalent capacitance) and load capacitance. Dynamic power dissipation is obtained by multiplying this current by the voltage applied to the P-channel or N-channel MOSFET. Here, for the sake of simplicity, the VCC value at which the maximum current flows is used for power calculation.
Dynamic power dissipation due to load capacitance (CL): PL
PL is dissipated when an external load is charged and discharged as shown by the right-hand figure.
The amount of charge (Q) stored on the load capacitance is calculated as follows:
QL = CL x VCC
CL: Load capacitance
Let the output signal frequency be fOUT (= 1/TOUT). Then, the average current (IL) is expressed as follows:
IL = QL / T = CL * VCC * fOUT
Hence, dynamic power dissipation (PL) is:
PL = VCC * IL ＝ CL * VCC^2 * fOUT
If an IC has multiple outputs, its dynamic power dissipation can be calculated as follows:
PL = VCC^2 * Σ（CLn* fOUTn）