3.1. Input offset voltage (V_IO)

Figure 3-3 shows the ideal op-amp without an offset voltage source (V_IO). When a common-mode input voltage is applied to V_IN(+) and V_IN(-) simultaneously, the output (V_o) voltage theoretically becomes V_DD/2. In reality, however, it has a small error from V_DD/2. The input offset voltage (V_IO) is the voltage applied between V_IN(+) and V_IN(-) required to reduce the V_o error to zero. The definition of the input offset voltage is similar to that of the common-mode input signal rejection ratio (CMRR) detailed in the next section.
In real-world applications, the input offset voltage multiplied by the closed-loop gain (A_CL) is added to the output voltage. Therefore, in the case of a sensor circuit, the maximum input offset voltage must be lower than its minimum sensitivity.

Let’s consider an op-amp with an input offset voltage of V_IO. As shown in the test circuit for the input offset voltage shown in Figure 3-3, this op-amp can be regarded as the ideal op-amp with an external V_Io voltage source connected to V_IN(-).
The V_IN(＋) voltage becomes V_DD/2. From the concept of a virtual short, the V_IN(-) voltage also becomes V_DD/2.
Therefore, the voltage at the intersection of R₁ and R₂ becomes V_DD/2 – V_IO. In the case of the ideal op-amp, I₁ = I₂.

I₁ = (V_DD/2 – V_IO – V_DD/2) / R₁ = - V_IO / R₁ = I₂
V_O = V_DD/2 – V_IO + (–V_IO / R₁) × R₂
= V_DD/2 – V_IO × (R₁ + R₂) / R₂

This can be rewritten as follows to calculate V_IO:

V_IO = (V_DD/2 – V_O) × R₁ / (R₁+ R₂)

Note that resistors have some tolerance. For actual measurement, the measured resistance values should be used.
V_IO is a differential voltage between V_IN(-) and V_IN(+). Therefore, when an op-amp is used with a closed loop, the voltage obtained by multiplying this input offset voltage (V_IO) by the closed loop-gain is added to the ideal output voltage. Since the V_O voltage varies from device to device, it is necessary to consider the maximum offset voltage when creating a circuit design. If it exceeds a system’s tolerance, it is necessary to modify the circuit configuration in such a manner as to reduce the effect of the input offset voltage or select an op-amp with a lower input offset voltage.

The AC-coupled circuit is the simplest form of circuit to reduce the effect of the input offset voltage. Figure 3-4 shows an AC-coupled inverting amplifier. When capacitor C₁ is connected in this way, current due to the input offset voltage does not flow through R₁. Therefore, the input offset voltage has a DC gain of 1 and thus has less effect on V_O.