Figure 3-3 shows the ideal op-amp without an offset voltage source (V_{IO}). When a common-mode input voltage is applied to V_{IN(+)} and V_{IN(-)} simultaneously, the output (V_{o}) voltage theoretically becomes V_{DD}/2. In reality, however, it has a small error from V_{DD}/2. The input offset voltage (V_{IO}) is the voltage applied between V_{IN(+)} and V_{IN(-)} required to reduce the V_{o} error to zero. The definition of the input offset voltage is similar to that of the common-mode input signal rejection ratio (CMRR) detailed in the next section.

In real-world applications, the input offset voltage multiplied by the closed-loop gain (A_{CL}) is added to the output voltage. Therefore, in the case of a sensor circuit, the maximum input offset voltage must be lower than its minimum sensitivity.

Let’s consider an op-amp with an input offset voltage of V_{IO}. As shown in the test circuit for the input offset voltage shown in Figure 3-3, this op-amp can be regarded as the ideal op-amp with an external V_{Io} voltage source connected to V_{IN(-)}.

The V_{IN(＋)} voltage becomes V_{DD}/2. From the concept of a virtual short, the V_{IN(-)} voltage also becomes V_{DD}/2.

Therefore, the voltage at the intersection of R_{1} and R_{2 }becomes V_{DD}/2 – V_{IO}. In the case of the ideal op-amp, I_{1} = I_{2}.

I_{1} = (V_{DD}/2 – V_{IO} – V_{DD}/2) / R_{1} = - V_{IO} / R_{1} = I_{2
}V_{O} = V_{DD}/2 – V_{IO} + (–V_{IO} / R_{1}) × R_{2
}= V_{DD}/2 – V_{IO} × (R_{1} + R_{2}) / R_{2}

This can be rewritten as follows to calculate V_{IO}:

V_{IO} = (V_{DD}/2 – V_{O}) × R_{1} / (R_{1}+ R_{2})

Note that resistors have some tolerance. For actual measurement, the measured resistance values should be used.

V_{IO} is a differential voltage between V_{IN(-)} and V_{IN(+)}. Therefore, when an op-amp is used with a closed loop, the voltage obtained by multiplying this input offset voltage (V_{IO}) by the closed loop-gain is added to the ideal output voltage. Since the V_{O} voltage varies from device to device, it is necessary to consider the maximum offset voltage when creating a circuit design. If it exceeds a system’s tolerance, it is necessary to modify the circuit configuration in such a manner as to reduce the effect of the input offset voltage or select an op-amp with a lower input offset voltage.

_{1} is connected in this way, current due to the input offset voltage does not flow through R_{1}. Therefore, the input offset voltage has a DC gain of 1 and thus has less effect on V_{O}.

3. Electrical characteristics

3.3. Internal noise of an op-amp

3.4. Noise gain and signal gain

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