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3.1. Input offset voltage (VIO)

Figure 3-3 Test circuit for the input offset voltage
Figure 3-3 Test circuit for the input offset voltage

Figure 3-3 shows the ideal op-amp without an offset voltage source (VIO). When a common-mode input voltage is applied to VIN(+) and VIN(-) simultaneously, the output (Vo) voltage theoretically becomes VDD/2. In reality, however, it has a small error from VDD/2. The input offset voltage (VIO) is the voltage applied between VIN(+) and VIN(-) required to reduce the Vo error to zero. The definition of the input offset voltage is similar to that of the common-mode input signal rejection ratio (CMRR) detailed in the next section.
In real-world applications, the input offset voltage multiplied by the closed-loop gain (ACL) is added to the output voltage. Therefore, in the case of a sensor circuit, the maximum input offset voltage must be lower than its minimum sensitivity.

Let’s consider an op-amp with an input offset voltage of VIO. As shown in the test circuit for the input offset voltage shown in Figure 3-3, this op-amp can be regarded as the ideal op-amp with an external VIo voltage source connected to VIN(-).
The VIN(+) voltage becomes VDD/2. From the concept of a virtual short, the VIN(-) voltage also becomes VDD/2.
Therefore, the voltage at the intersection of R1 and R2 becomes VDD/2 – VIO. In the case of the ideal op-amp, I1 = I2.

I1 = (VDD/2 – VIO – VDD/2) / R1 = - VIO / R1 = I2
VO = VDD/2 – VIO + (–VIO / R1) × R2
= VDD/2 – VIO × (R1 + R2) / R2

This can be rewritten as follows to calculate VIO:

VIO = (VDD/2 – VO) × R1 / (R1+ R2)

Note that resistors have some tolerance. For actual measurement, the measured resistance values should be used.
VIO is a differential voltage between VIN(-) and VIN(+). Therefore, when an op-amp is used with a closed loop, the voltage obtained by multiplying this input offset voltage (VIO) by the closed loop-gain is added to the ideal output voltage. Since the VO voltage varies from device to device, it is necessary to consider the maximum offset voltage when creating a circuit design. If it exceeds a system’s tolerance, it is necessary to modify the circuit configuration in such a manner as to reduce the effect of the input offset voltage or select an op-amp with a lower input offset voltage.

Figure 3-4 AC-coupled inverting amplifier
Figure 3-4 AC-coupled inverting amplifier

The AC-coupled circuit is the simplest form of circuit to reduce the effect of the input offset voltage. Figure 3-4 shows an AC-coupled inverting amplifier. When capacitor C1 is connected in this way, current due to the input offset voltage does not flow through R1. Therefore, the input offset voltage has a DC gain of 1 and thus has less effect on VO.

Related information

Chapter3 Electrical characteristics

3. Electrical characteristics
3.2. Common-mode input voltage range (CMVIN) and common-mode input signal rejection ratio (CMRR)
3.3. Internal noise of an op-amp
3.4. Noise gain and signal gain

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