# Countermeasures for Signal Reflection

In the case of high-speed CMOS logic ICs, reflections cause an increase in the signal delay, ringing, overshoot, and undershoot. Reflections in transmission lines:

Typical traces have a characteristic impedance(*1) of 50 to 150 Ω. However, the I/O impedance of high-speed CMOS logic ICs differs from the typical characteristic impedance of traces. This impedance mismatch causes part of the transmitted signal to be reflected to both the transmitting and receiving ends of a transmission line.
Signal reflection does not affect a slowly rising output because its rise period overlaps that of the reflected signal.
Signal reflection causes a problem when the reflected signal returns to the output after it rises, i.e., when the following equation is true:

tr < 2T
tr: Rise time of the output signal
T: Propagation delay time from the transmitting end to the receiving end of a transmission line

Suppose that the output rise time is 3 ns and that the propagation delay time along a transmission line is 5 ns/m.
Then, signal reflection has a significant impact when the transmission line is 30 cm or longer.

*1 Characteristic impedance
The characteristic impedance is one of the characteristics of a transmission line (e.g., board trace, coaxial cable).
The general expression of the characteristic impedance of a transmission line is Z_0=√(L/C), where L is the inductance per unit length and C is the capacitance per unit length. The unit of characteristic impedance is ohm (Ω). When a termination resistor of 50 Ω is connected to the end of a transmission line with a characteristic impedance of 50 Ω, signal reflection does not occur at the connection point.
However, if the characteristic impedance does not match the resistor value, signal reflection occurs at the connection  point.

Countermeasures to reduce Signal Reflection
(1) Increase the board assembly density and reduce the length of board traces to reduce their inductance and capacitance. In this case, however, care is required as to crosstalk between adjacent traces. (See the next page for crosstalk.)
(2) Do not use ICs with an output current higher than necessary.
(3) Provide electrical termination so that the I/O impedance of a CMOS logic IC matches the characteristic impedance of the transmission line (See blow figure).

(4) When the output of a CMOS logic IC drives multiple CMOS logic ICs the output trace should be fanned out close to the driven ICs.

## Usage Considerations of CMOS Logic ICs

Handling of Unused Input Pins
Input Rise and Fall Time Specifications
Multiple Outputs from a General-Purpose CMOS Logic IC Come Into Conflict (Short-Circuiting)
Connecting a Load Capacitance to a CMOS Output Pin
Calculating the Operating Supply Current and Power Dissipation
Level Shifting Using an Input-Tolerant Function
Example of Application of the Power-Down Protection Function (Partial Power-Down)
Input-Tolerant and Output Power-Down Protection Functions Available with Each Series
Types of Noise to be Noted
Countermeasures for Reducing Switching Noise
Countermeasures for Crosstalk
Countermeasures for Hazards
Countermeasures for Metastability
Countermeasures for Latch-Up
Countermeasures for ESD Protection

## Related information

• Application Notes
• FAQ
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