Countermeasures for Metastability

The output of a synchronous sequential circuit can potentially persist in an unstable equilibrium called a metastable state, depending on the timing of a data signal to be latched relative to the clock signal.
A sequential circuit enters a metastable state when its input setup and hold time (t_s and t_h) requirements shown in the datasheet are not satisfied.

Metastability potentially occurs when an active input (e.g., a clock signal) and a passive input (e.g., a data signal) are asynchronous to each other. To prevent sequential circuits from entering a metastable state, the recommended timing conditions shown in the datasheet must be satisfied.
For example, when the CK and D inputs are asynchronous, they can be synchronized as shown below.
In this case, however, care should be exercised as to the cycle period and propagation delay of CK.
If they are close, the data signal might not propagate to the second flip-flop.
The synchronizer shown in Figure 5.3 consists of two flip-flops. The first flip-flop prevents an increase in t_pd and a hazard from being transferred to the output of the second flip-flop.
Even in this case, care is needed when the phase difference between CK1 and CK2 is close to the CK-to-Q delay (t_pd) of the first flip-flop.