Connecting a Load Capacitance to a CMOS Output Pin

When an output pin of a CMOS IC is connected directly to a large load capacitance, its propagation delay increases. In addition, the increased charge/discharge current into or out of the capacitor might cause noise or a bonding wire burnout. Since current flows to the output parasitic diode at power-down, a CMOS IC should not be connected directly to a large load capacitance.
If it is necessary to connect a capacitor directly to the output of a CMOS IC in order to increase its delay time or filter out noise, its capacitance should be 500 pF or less. When a larger capacitor is required, a current-limiting resistor (R) should be connected between the IC output and a capacitor as shown below. CMOS ICs with an output-tolerant function do not need a current-limiting resistor (R) for power-down. However, a current-limiting resistor (R) might be necessary to limit the charge current into the capacitor. 

When a capacitor is discharged as a result of power-down, current flows to an internal protection diode returned to V_CC via the input pin.
In the case of an input pin, current flows to an internal protection diode returned to V_CC  when a capacitor is discharged as a result of power-down.
Therefore, a large load capacitance should not also be connected directly to an input pin. A capacitor of up to 500 pF may be connected directly to the input of a CMOS IC, but when a larger capacitor is required, a current-limiting resistor (R_s) should be connected between the IC input and a capacitor as shown below.