Part Number Search

Cross Reference Search

About information presented in this cross reference

The information presented in this cross reference is based on TOSHIBA's selection criteria and should be treated as a suggestion only. Please carefully review the latest versions of all relevant information on the TOSHIBA products, including without limitation data sheets and validate all operating parameters of the TOSHIBA products to ensure that the suggested TOSHIBA products are truly compatible with your design and application.
Please note that this cross reference is based on TOSHIBA's estimate of compatibility with other manufacturers' products, based on other manufacturers' published data, at the time the data was collected.
TOSHIBA is not responsible for any incorrect or incomplete information. Information is subject to change at any time without notice.

Keyword Search

Parametric Search

Stock Check & Purchase

Select Product Categories

Connecting a Load Capacitance to a CMOS Output Pin

Connecting a large load capacitance
Connecting a large load capacitance

When an output pin of a CMOS IC is connected directly to a large load capacitance, its propagation delay increases. In addition, the increased charge/discharge current into or out of the capacitor might cause noise or a bonding wire burnout. Since current flows to the output parasitic diode at power-down, a CMOS IC should not be connected directly to a large load capacitance.
If it is necessary to connect a capacitor directly to the output of a CMOS IC in order to increase its delay time or filter out noise, its capacitance should be 500 pF or less. When a larger capacitor is required, a current-limiting resistor (R) should be connected between the IC output and a capacitor as shown below. CMOS ICs with an output-tolerant function do not need a current-limiting resistor (R) for power-down. However, a current-limiting resistor (R) might be necessary to limit the charge current into the capacitor. 

When a capacitor is discharged as a result of power-down, current flows to an internal protection diode returned to VCC via the input pin.
In the case of an input pin, current flows to an internal protection diode returned to VCC  when a capacitor is discharged as a result of power-down.
Therefore, a large load capacitance should not also be connected directly to an input pin. A capacitor of up to 500 pF may be connected directly to the input of a CMOS IC, but when a larger capacitor is required, a current-limiting resistor (Rs) should be connected between the IC input and a capacitor as shown below.

Usage Considerations of CMOS Logic ICs

Handling of Unused Input Pins
Input Rise and Fall Time Specifications
Multiple Outputs from a General-Purpose CMOS Logic IC Come Into Conflict (Short-Circuiting)
Calculating the Operating Supply Current and Power Dissipation
Level Shifting Using an Input-Tolerant Function
Example of Application of the Power-Down Protection Function (Partial Power-Down)
Input-Tolerant and Output Power-Down Protection Functions Available with Each Series
Types of Noise to be Noted
Countermeasures for Reducing Switching Noise
Countermeasures for Signal Reflection
Countermeasures for Crosstalk
Countermeasures for Hazards
Countermeasures for Metastability
Countermeasures for Latch-Up
Countermeasures for ESD Protection

Products

Related information

A new window will open