How to calculate the allowable power dissipation of a bias resistor built-in transistor (BRT)

The power dissipation of a BRT is the sum of the power dissipated by the internal transistor (Q) and the built-in bias resistors (R₁ and R₂).

Here, let’s calculate the power dissipated by the BRT shown in Figure 1 when it is in the “on” state.
Suppose that the BRT is the RN1402 (R₁=R₂=10 kΩ), the input voltage (V_I) is 10 V, the collector-emitter voltage (V_CE) is 0.2 V, the base-emitter voltage (V_be) is 0.7 V, and the operating current gain (h_FE) of the internal transistor is 10.

Then, I_B, I_R2, I_b, and I_C are calculated as follows:
    I_B = ( V_I – V_be ) / R₁ = ( 10 – 0.7 ) / 10 = 0.93 mA
    I_R2 = V_be / R₂ = 0.7 / 10 = 0.07 mA
    I_b = I_B – I_R2 = 0.93 – 0.07 = 0.86 mA
    I_C = I_b * h_FE = 0.86 * 10 = 8.60 mA

Let the power dissipation of R₁ and R₂ be P_R1 and P_R2 respectively and the collector-emitter and base-emitter power dissipation of the transistor be P_CE and P_be respectively.
    R₁: P_R1 = ( V_I – V_be ) * I_R1 = ( 10 – 0.7) * 0.93 = 8.65 mW
    R₂: P_R2 = V_be * I_R2 = 0.7 * 0.007 = 0.05 mW
    V_CE: P_CE = V_CE * I_C = 0.2 * 8.6 = 1.72 mW
    V_be: P_be = V_be * I_b = 0.7 * 0.86 = 0.60 mW

Hence, the power dissipation (P) of the BRT is calculated as:
    P = P_R1 + P_R2 + P_CE + P_be = 11.02 mW