Operation Mode and Stack Pointer (1)

Arm® Cortex®-M3 has two privileged levels (Privilege/Non-privilege) and two operation modes (Thread/Handler).
For embedded usage, a basic configuration with only privileged level or a configuration to switch between Privilege and Non-privilege can be selected.
At the privileged/non-privileged level, by switching between the main stack (MSP) and process stack (PSP) assigned to register R13, the stack area can be separated and managed by processing functions such as the OS kernel and user routines.

Basic system
System using RTOS

Chapter 2 Arm® Cortex®-M3

Hardware Configuration
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NVIC (Nested Vectored Interrupt Controller)
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Main Core
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Register Configuration
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The Role of the Register
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PC, LR
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Stack Pointer
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PUSH/POP to the Stack Pointer
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Special Register
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Operation Mode and Stack Pointer (2)
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Exceptions (Reset, Interrupt, Fault, System Call)
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The Role of NVIC
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Tail Chain Control by NVIC
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Memory Map
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Memory Map for Arm® Cortex®-M3 Specifications
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Memory Map of TMPM330: Example of TX03 Series
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Vector Table (1)
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Vector Table (2)
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Bit Band Area and Bit Band Alias Area (1)
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Bit Band Area and Bit Band Alias Area (2)
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